Pseudo differential multi-cell upset immune

robust SRAM cell for ultra-low

power applications
DIGITAL SIGNAL PROCESSING

RESEARCHER: KAZEM KHAARI

PROFESSOR: DR.ARDALANI

ISLAMIC AZAD UNIVERSITY ( SCIENCE AND RESEARCH BRANCH)

 Introduction
SRAM is an important building block in computing systems

SRAM almost occupy more than 50% of the chip area.

It can be used in low power applications like wireless sensor nodes,

implantable biomedical devices .

We operate SRAM in near/sub-threshold region for reduce leakage and

active power.

Read/Write failure probability has been increased

Soft-error :reduction of critical charge

Single-event upsets (SEUs) and multiple-cell upsets (MCUs).

interleaving architecture results into Half Select (HS)

HS issue is handled by techniques such as write-back array architecture

approach local write wordline and hard-coding etc.
12T bit-interleaving cell, BI12T and a power gated 9T cell, PG9T have been
proposed to solve the HS issue without using these techniques.

BI12T suffers with very precise WL pulse.

Proposed PD12 T is using only bit interleaving technique.

bit-interleaving architecture to improve MCUs immunity.

improves write-ability without using additional peripheral write-assist circuits

It is suitable for all-TFET implementation.

In Section 2, cell structure and functioning of PD12T is discussed. Section 3 presents

the simulation setup, results and comparison of the SRAM cells considered in this
work and Section 4 concludes this paper
2. Pseudo differential 12T (PD12T) SRAM cell
Fig.2 shows the schematic diagram of the proposed PD12T SRAM
cell.

The PD12T cell consists of a cell core(cross coupled inverter ),read

and write access .

Read operation

Write operation
3. Simulation results and discussion
Simulation setup
We use HSPICE and 16 nm CMOS Technology Model.

Proposed cell minimized the area and leakage overhead by

using minimum size transistors.

36 nm width for both read and write access transistors to

reduce
the delays. Monte Carlo methods, or Monte Carlo
experiments, are a broad class of
we perform Monte Carlo simulations with a sample size of computational algorithms that rely on
5000 to analyze the impact of process variations repeated random sampling to obtain
numerical results.
we take into account the variations in channel length (L),
channel width(W),channel doping concentration(NDEP),and oxide
thickness (Tox)
Hold SNM
Hold SNM or HSNM is a measure of the stability of the
SRAM cell in standby mode.

the maximum value of DC noise voltage that can be

sustained by an SRAM cell without altering the stored bit
during hold mode.

The HSNM is determined by the length of the side of the

largest square that can be inscribed between these two
curves.

The HSNM of PD12T is marginally better than 6T because of

stacked PMOS transistors.

Schmitt-trigger in s2 . The HSNM depends on Temperature .

Read stability
The proposed cell uses separate read buffer . we don’t have upset issue.

stability is same as the hold stability.

graphically estimated as the length of a side of the largest square that

can be embedded inside the smaller lobe of the butterfly curve.

We observe that the proposed cell offers 50% improvement in the mean
value of RSNM as compared with the ST-2 cell. When compared with
CHANG10T and BI12T cells, the PD12T cell gives 1.14× and 1.1×
larger value of mean RSNM.
Write ability
Write Margin technique is better than VTC SNM approach to
measure the write ability.

Write Margin (WM) is defined as the difference between

VDD and WL voltage at which the nodes
Q and QB flip.

A higher value of WM indicates the ease of writing

into the cell.

the two WMs for write ‘0’ and write ‘1’ are same for
differential cells.

power cut-off technique used in pd12t and bi 12t .

Read/write access time
Read access time or read delay (TRA) is the time duration
between the RWL activation to the instant when the ‘RBL’
voltage is discharged by 50 mV from its initial high level
value.

Single ended read is (VDD – 50 mV).

Write access time or write delay (TWA) for writing ‘1’ is

estimated as the time duration between the WWL activation
time to the time when a ‘0’ storing node charges up to 90% of
VDD.(write zero )

The BI12T and PD12T cells have relatively higher TWA as

compared to 6T, CONV8T, CHANG10T and ST-2.
Read/write power consumption
There is always a trade-off between power and delay.

The cells like CONV8T, CHANG10T and PD12T consume

higher power during read operation.

The proposed PD12T cell consumes least

write power at all the supply voltages.

the PD12T cell shows 53% reduction in the write power as

compared to 6T cell at 0.5 V supply voltage.
Leakage power
Leakage power contributes largely to the total power
dissipation in an SRAM cell.

As technology scales to nanometer the subthreshold leakage

in embedded memory becomes a serious issue.

plots the mean and standard deviation of leakage power of

SRAM cells at their VDD min, in the presence of local and
global process variations, which is determined by MC
simulation with 20,000 samples at temperature 50 °C and at
FF worst
case leakage corner.

The least leakage power characteristic

of the proposed cell holds potential to significantly reduce
the overall power consumption of embedded memories.
Ion-Ioff ratio of read path
Number of SRAM cells that can be connected to a given bitline in an
array is often dictated by the Ion/Ioff ratio

We measure the Ion as the average current during read

access time for a cell and Ioff through access transistor in hold mode.

proposed SRAM cell is second best from Ion/Ioff ratio point of view.

As compared to 6T SRAM, PD12T offers more than 10× higher

Ion/Ioff ratio for the read path at 0.7 V.

This is because of the use of RWLB control signal in the read path.
Minimum supply voltage (VDD, min)
The minimum supply voltage (VDD,min) of an SRAM
cell is the voltage at which HSNM and RSNM is at least
26 mV and Write Margin is positive.

The PD12T cell offers minimum value of VDD,min

among all the considered cells.

compared with 6T cell, PD12T cell successfully

operates at 65% smaller VDD. because of the
improvement in the RSNM, HSNM and WM.

Smaller value of VDD,min holds great potential towards

saving of leakage power and thus overall power
consumption.
Soft error rate
Soft error in SRAM cell occurs when a high energy particle
from cosmic radiation or chip packaging materials causes
enough of a charge disturbance to flip the data of the storage
node. Ipeak is the current pulse amplitude, τr is the rising
time constant and τf the falling time constant.
The soft error tolerance of an SRAM cell can evaluated from
its critical charge, Qcri

where Nflux is the intensity of the neutron flux, A is the

cross section area of the node and Qs is the charge
collection efficiency of the device,
in fC.

We estimate Qcrit of an SRAM cell by circuit simulation

using double current source model for the charge
collection.
Fig shows the critical charge of SRAM cells
computed at VDD = 0.7 V and 0.35 v.

It is observed that the proposed PD12T cell shows

highest critical charge among the considered cells.

PD12T cell achieves 15% and 18% improvement in

Qcrit over 6T cell at
VDD = 0.7 V and 0.35 V.

This paper reports the worst case Qcrit, which is for

the case of Q = 1 for these two cells.
Bit interleaving
SRAM cells usually have the lowest Qcrit among all
other memory elements

Bit- interleaving (BI) technique ,is used to deal with

MCUs errors efficiently.

Fig. 14 shows the distribution plot of

the Hold SNM for both the row and column HS cells,
which confirms that the bit-cell can function properly in
HS state.

Therefore, the proposed cell PD12T can easily be

integrated in a bit-interleaving architecture without the
need of write-back or any other assist scheme.

the PD12T cell has highest Qcrit and when implemented

in BI fashion will achieve high
MCU immunity.
 Area comparison
the layout view of 6T, BI12T and the proposed
PD12Tcells designed using 45 nm technology rules.

The cell areas are normalized with respect to 6T

SRAM cell. Table 3 presents the comparison of
relative area and some other features of several
SRAM cells considered in this work.
Electrical Quality Metric (EQM)
to comprehensively assess the performance of
an SRAM cell, we utilize Electrical Quality Metric (EQM) to
evaluate the overall quality of a cell. EQM is defined as:

where Read SNM and Hold SNM are the static noise margin
during hold and read operation. WM is the Write Margin of the
cell. Read delay is the read access time. Pleak is the average
leakage power. Pread and Pwrite are the dynamic power of the
cell during read and write operation.

proposed PD12T cell has the best EQM at all supply voltages. It
is an attractive choice considering the overall performance
along with high SNM and Qcrit at lower supply voltages.
Conclusion
This work proposed a fully half-select-free robust low-power 12T
SRAM cell that is suitable for bit-interleaved architecture.

PD12T cell eliminates Read disturb and improves the Write-ability

by using power-cutoff and Pseudo-Differential Write-Assist.

The proposed cell achieves 18% and 26% higher Qcrit compared
with 6T and BI12T cell.

The proposed cell is also suitable for all-TFET implementation as it

uses only unidirectional transistors

the proposed cell could be good circuit solution for ultralow voltage
moderate speed applications that demands high stability.
Thank you for your time and consideration