AJAY G 1BG10LVS01 Batch-2010 Phase I Feasibility study and project groundwork

Project Guides:
External guide : Prof .KUMAR M.N Executive Director, GM . TranSwitch India Internal Guide: DR. VEENA S CHAKRAVARTHI Professor, Dept., Of E&C B.N.M.I.T

M.Tech. VLSI Design & Embedded Systems Department of Electronics & Communication Engineering BNM Institute of Technology www.bnmit.org

Motivation Specific Aim and Project Topic Introduction The Project approach Implementation Flow Project Stages Project Timelines Current Status Result Expectations and Possibilities Identified forums to share the results Q 7/10/2011 & A AJAY G 1BG10LVS01 BNMIT

As the feature size of MOSFETs are decreasing readily, new standard cell library must be developed for each technology node Also, at VDSM many second order effects occur Hence , the project is of particular interest to understand the Standard cell library design flow and deal with issues emerging at VDSM
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Developing a optimized library using Cadence analog tools ,and hence ,

To understand the standard cell library development

process To deal with issues emerging at VDSM technology. To study various optimizing techniques required.

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Standard Cell Library Design flow Standard cell components Standard cell library formats Cell views

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Design Entry Library Verification

Pre Layout Simulation

Layout

Characterization

Post Layout Simulation

Abstract Standard Cell Library

Extraction
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Power & timing info

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The standard cells can be categorized into

Gates Flip Flops IO Cells

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CELL NAME INV BUFFER AND OR NAND NOR AOI OAI XOR XNOR HALF ADDER MUX
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N0., OF INPUTS 1 1 2,3 2,3 2,3 2,3 2X2,3X3 2X2,3X3 2 2 2 2X1

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DRIVE STRENGTH 1X,2X,4X,16X 1X,2X,4X,16X 1X,2X,4X 1X,2X,4X 1X,2X,4X 1X,2X,4X 1X,2X,4X 1X,2X,4X 1X 1X 1X,2X 1X,2X
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CELL NAME D FLIPFLOP LOW ENABLE LATCH HIGH ENABLE LATCH CLKGATE TRISTATE BUFFER TRISTATE INVERTER FILLER CELLS

DRIVE STRENGTH 1X,2X 1X,2X 1X,2X 1X,2X 1X,2X,4X 1X,2X,4X

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.lef Layout Exchange Format

Using Cadence Abstract Generator

.lib Liberty library format

Using Cadence ELC

.spi Spice netlist .v Verilog model .sdf - Standard delay format .html or .ps - databook
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Layout view Abstract view Schematic view Symbol view

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Schematic Cadence Virtuoso

Pre Layout Simulation Cadence Spectre

Layout generation

Cadence Virtuoso Layout XL

Post Layout Simulation Cadence Spectre Simulator

Cell Characterization Standard Cell library Cadence Encounter Library Characterizer

Extraction Cadence QRCx

Abstract Generation Cadence Abstract generator

Cell Library Documentation

Cell Liibrary Verification Cadence Digital design suite

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Optimization:
Low Power , low leakage cells

Implementing cells of various drive strength and maintaining a power budget Accurate modeling during characterization VDSM Geometry associated issues

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Stage 1 : Standard Cell Design & Verification Stage 2 : Cell Library characterization Stage 3: Cell Library Verification Stage 4: Documentation

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Cell Schematic Entry Pre Layout Simulation Cell Layout generation Post Layout simulation

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Spice netlist Generation Cell Characterization:

Involves extraction of timing information for

different process ,temperature and voltage parameters based on the foundry data

Model generation of standard cells

Generation of different views /formats required

for different levels of digital design tools

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The cell library will be verified by implementing the ISCAS85 C880 benchmark circuit

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After the characterization of the std. cell, it is verified for different parameters by building a design from it The same design is again implemented with the Cadence standard cell library The two implementations are then compared to benchmark the low power optimization.

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Prepare a proper Datasheet for the Standard cell library developed Preparation of Project Report

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Have designed and generated layouts for:

Inverter circuit with 1X, 2X, 4X drive strengths. 2 input NOR & NAND with 1x drive strengths.

Parallelly going through power optimization techniques.

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STAGE 1 Cell Design Entry Upto November31

STAGE 2
Cell Library Characterization December to January STAGE 3 Cell Library verification February STAGE 4 Documentation March

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The deliverables of this project are

A working Optimized Standard Cell library A Databook documenting the characteristics of

the Standard Cell library A Sequential and combinational Implementation using the standard cell library developed.

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International Conference on Devices, Circuits and Systems ICDCS 2012. Mar 15-16, 2012 in Karunya University

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Thank You

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