HDL Lecture4

Hardware Description
Languages
Professor: Sci.D., Professor

Vazgen Melikyan
Synopsys University Courseware

Copyright © 2014 Synopsys, Inc. All rights reserved.
Hardware Description Languages
Lecture - 4
1 Developed By: Vazgen Melikyan
Course Overview
 The Role and Classification of HDLs

 1 lecture
 System Verilog
 2 lectures
 SystemC
 3 lectures
 Verilog
 4 lectures
 VHDL
 3 lectures
 Process of Synthesis
 2 lectures

Lecture - 4
Developed By: Vazgen Melikyan
2
Verilog

Lecture - 4
3 Developed By: Vazgen Melikyan
Overview
 Verilog
 Modeling concept
 Basic concept
 Behavioral modeling
 Data flow modeling
 Gate level modeling
 Switch level modeling
 Testbench creation
 Tasks and functions

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Overview: Modeling Concept
 Verilog
 Basic concept

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Levels of Abstraction
 Behavioral
 The highest level of abstraction provided by Verilog HDL. A module is
implemented in terms of the desired design algorithm
 Data Flow
 At this level the module is designed by specifying the data flow
 Gate Level
 The module is implemented in terms of logic gates and interconnections
between these gates
 Switch Level
 This is the lowest level of abstraction provided by Verilog. A module can
be implemented in terms of switches, storage nodes and the
interconnections between them

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Design Methodologies
 Top-Down Design
 Define the top-level block
 Identify the sub-blocks
necessary to build the top-level
block
 Sub-blocks are formed by leaf
cells which cannot be further
divided
 Bottom-up Design
 Build macro cells using leaf
cells
 Move up the hierarchy until the
top-level is reached

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Overview: Basic Concept
 Verilog
 Basic concept

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Module
 Module
 Basic building block
 Only user-declared object type
 Element or a collection of lower level design blocks

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Module Header Format
Traditional header format Newer header format

module module count(output Cout,
count(Cout,Cin,clk); input Cin, clk);
input Cin, clk;
reg CoutR;
output Cout;
assign Cout=CoutR;
reg Cout;
……. ………
endmodule endmodule

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Lexical Conventions
 Comments
 Numbers
 Strings
 Identifier
 Operators

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Lexical Conventions: Comments
Comments
Syntax Example
One line comment- //comment sum=a+b // This is a one line
Multiple line comment- /*comment*/ comment
d[1]=1’b0; /* d[0]=1’b1;
This is a multiple-line
comment block */

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Lexical Conventions: Identifiers
 Identifiers
 Names given to objects
 Cannot start with a number or dollar sign ($)
 Can start with alphabetic character or underscore
wire a1; // wire is a keyword, a1 is an identifier

output sum; // output is a keyword, sum is an identifier

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Lexical Conventions: Numbers
 Sized numbers <size>`<base

format><number>
 5`b10111 // 5-bit binary number
 16`hcdab // 16-bit hexadecimal number
 3`d7 // 3-bit decimal number
 Unsized numbers
 16549 // 32-bit decimal number by default
 `o21 // 32-bit octal number

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Lexical Conventions: Numbers (2)
 x or z values
 x – unknown value
 z – high impedance value
 16`h536x // This is a 16-bit hexadecimal value with 4
least significant bits unknown
 Negative numbers
 Number with a minus sign before the size of a
constant number
 -10`d9
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Lexical Conventions: Numbers (3)
 Underscore, Question mark

 “_” character – anywhere in a number except the first
character
 16`b1010_0110_1101
 “?” question mark – substitutes z in numbers for better
readability
 8`b111?

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Lexical Conventions: Strings
 Strings
 Any characters enclosed by double quotes
 “Verilog HDL Concepts”

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Data Types
 Nets
 Vectors
 Registers
 Arrays

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Data Types: Nets
Name Keyword Default value Default size

net wire, supply0, z 1bit
supply1
Example
wire net1;
wire net2, net4;
supply0 vss;

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Data Types: Registers
Name Keyword Default value Default size

register reg x 1bit
Example
reg register1;
reg register2,
register3;

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Data Types: Vectors
 Wire or register which is more than 1 bit in

size
 Definition syntax
 <data type> [<start>:<end>] <identifer>
 Reference syntax
 <variable_name>{array_reference}
Example
reg [3:0] output; // output is a 4-bit register
wire [31:0] data; // data is a 32-bit wire
reg [7:0] a;
data[3:0] = output; // partial assignment
output = 4'b0101; // assignment to the whole register
data[24]; // referencing to 24th bit

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Data Types: Arrays
 Array
 Definition syntax
 <data_type_spec> {size} <variable_name> {array_size}
 Reference syntax
 <variable_name> {array_reference} {bit_reference}
Example
reg data [7:0]; // 8 1-bit data elements

integer [3:0] out [31:0]; // 32 4-bit output
elements
out[3][27]; // referencing bit number 27 in the
3rd element

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Parameter Types
 Parameters
 Parameters are unsigned integer constants by default
 Must be assigned when declared. Width defaults are
enough for the value assigned
 May be declared signed (but many tools reject it)
 May be declared real (but not synthesizable)
 May be typed by vector index range
 Declaration allowed anywhere in module, but local
parameter proffered in body

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Lexical Conventions: Operators
 Operators
 Unary operators
 stand before the operand
 Binary operators
 stand between two operands
 Ternary operators
 have two separate operators that separate three operands

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Operator Types
Operator Type Operator
Arithmetic operators *, /, +, -, %
Logical operators &&, ||, !
Relational operators >, <, >=, <=
Equality = =, !=, = = =, != =
Bitwise operators ~, &, |, ^, (~^, ^~)
Reduction Operator &, ~&, |, ~|, ^, ~^, ^~
Shift Operator >>, <<
Concatenation {, }
Replication c = {4{a}}
Conditional ?:

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Operator Precedence
Operators Operator Symbols Highest Precedence
Unary +-!~
Multiply, Divide, Modulus */%
Add, Subtract +-
Shift << >>
Relational < <= > >=
Equality == != === !==
Reduction &, ~&
^, ^~
|, ~|
Logical &&
||
Lowest Precedence
Conditional ?:
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Sequential Blocks
 Sequential Blocks
 Statements in a sequential block are processed in the
order they are specified
 A statement is executed only after its preceding
statement completes execution (except for non-
blocking assignments)
 If delay or event control is specified it is relative to the
simulation time, i.e. execution of the previous
statement

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Parallel Blocks
 Statements in a parallel block are executed

concurrently
 Ordering of statements is controlled by the
delay or event control assigned to each
statement
 If delay or event control is specified, it is
relative to the time the block was entered

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Comparison of Sequential and
Parallel Blocks
 Fundamental difference between sequential
and parallel blocks:
 All statements in a parallel block start at the time when
the block was entered
 Thus, the order in which the statements are written in
the block is not important

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Parallel Blocks (2)
Example
reg x, y;
reg [1:0] z, w;
initial
fork
x = 1'b0;
#5 y = 1'b1; x completes at simulation time 0
y completes at simulation time 5
#10 z = {x, y}; z completes at simulation time 10
#20 w = {y, x}; w completes at simulation time 20
join

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Basic Compiler Directives
 Syntax: `<keyword> Example:

 `define MAX 16`b1111111111111111;
 The given 16-bit number will be substituted wherever `MAX
appears
 `include integrator.v
 Includes the contents of Verilog source file in another Verilog
file during compilation
 `timescale <reference time unit>/<time_precision>
 <reference time unit> specifies the unit of measurement for
times and delays
 <time_precision> specifies the precision to which the delays
are rounded off during simulation
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Overview: Behavioral Modeling
 Verilog
 Basic concept

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Behavioral Modeling Blocks
 Blocks
 Always
 Event-based timing control
 Branch
 Case, casex, casez

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Behavioral Modeling Blocks:
Always Block
Syntax Example
always operation_name module pulse;
reg clock;
initial clock = 1'b0; // start the clock at 0
always #10 clock = ~clock; /* toggle every 10 time
units*/
endmodule

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Event-based Timing Control
Syntax Example
@(event) op_name @ (clock) a = b;
when the clock changes value, execute a = b
@ (negedge clock) a = b;
when the clock change to a 0, execute a=b
a = @(posedge clock) b;
evaluate b immediately and assign to a on a
positive clock edge.

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Branch Statements
Syntax Example
if (conditional_expression) if (x!=1) a=2; else a=5
statement{ else statement}

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Behavioral Modeling Blocks: Case
Syntax Example
case(op) case(S3)
op1:operation1 00:A=00
default:operation5 default:operation5
endcase endcase

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Behavioral Modeling Blocks: casex,
casez
 Two variations of the reg [3:0] encoding;
integer state;
case statement casex (encoding)
4'b1xxx : next_state = 3;
 casez 4'bx1xx : next_state = 2;
4'bxx1x : next_state = 1;
 Treats all z values in the 4'bxxx1 : next_state = 0;
case alternatives or the default : next_state = 0;
case expression as don't endcase
cares, all bit positions with z
can also be represented by
? in that position
 casex  An input encoding =
 Treats all x and z values in 4'b10xz would cause
the case item or the case next_state = 3 to be
expression as don't cares executed
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Behavioral Modeling
 Definition of blocking and non-blocking procedural assignments

 Delay-based timing control mechanism in behavioral modeling
 The significance of structured procedures always and initial in
behavioral modeling
 Event-based timing control mechanism in behavioral modeling
 Level-sensitive timing control mechanism in behavioral modeling
 Conditional statements using if and else
 Multiway branching, using case, casex, and casez statements
 Looping statements while, for, repeat, and forever
 Sequential and parallel blocks

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Procedural Assignments
 Update values of reg, integer, real, or time

variables
 Blocking
 Non-blocking

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Procedural Assignments: Blocking
Assignments
 Blocking assignment statements are
executed in the order they are specified in a
sequential block
 A blocking assignment will not block
execution of statements that follow in a
parallel block
 The = operator is used to specify blocking
assignments
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Procedural Assignments: Blocking
Assignments (2)
Example
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
Initial Executed at time zero
begin
x = 0; y = 1; z = 1;
count = 0;
reg_a = 16'b0; Executed at time 15
reg_b = reg_a;
#15 reg_a[2] = 1'b1;
Executed at time 25
#10 reg_b[15:13] = {x, y, z}
count = count + 1;
//Assignment to an integer (increment)
end

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Procedural Assignments: Non-
Blocking Assignments
 Non-blocking assignments allow scheduling
of assignments without blocking execution of
the statements that follow in a sequential
block
 A <= operator is used to specify non-blocking
assignments

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Procedural Assignments: Non-
Blocking Assignments (2)
Example
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
Executed at time zero
initial
begin
x = 0; y = 1; z = 1;
count = 0;
reg_a = 16'b0;
reg_b = reg_a;
Executed at time 15
reg_a[2] <= #15 1'b1;

Executed at time 10
reg_b[15:13] <= #10 {x, y, z};

Executed at time zero
count <= count + 1;
end Synopsys University Courseware

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Implementation of a 4 to 1
Multiplexor Using if Statement
module multiplexor4_1 (out, in1, in2, in3 ,in4, cntrl1,

cntrl2);
output out;
input in1, in2, in3, in4, cntrl1, cntrl2;
reg out; // Note that this is now a register
always @(in1 or in2 or in3 or in4 or cntrl1 or cntrl2)
if (cntrl1==1)
if (cntrl2==1)
out = in4;
else out = in3;
else
if (cntrl2==1)
out = in2;
else out = in1;
endmodule

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Implementation of a 4 to 1
Multiplexor Using Case Statement
module multiplexor4_1 (out, in1, in2, in3, in4, cntrl1, cntrl2);

output out;
reg out; // note must be a register
always @(in1 | in2 | in3 | in4 | cntrl1 | cntrl2)
case ({cntrl2, cntrl1}) // concatenation
2'b00 : out = in1;
2'b01 : out = in2;
2'b10 : out = in3;
2'b11 : out = in4;
default : $display("Please check control bits");
endcase
endmodule

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Overview: Data Flow Modeling
 Verilog
 Basic concept

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Data Flow Modeling
 Describe the continuous assignment (assign)

statement
 Assignment delay, implicit assignment delay,
net declaration delay
 Expressions, operators, operands (already
mentioned)
 Examples of digital circuits modeling in
Verilog
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Assign Statement
 assign out = in1 & in2;

 Continuous assign
 Out is a net
 i1 and i2 are nets
 assign addit[15:0] = addit1[15:0] ^ addit2[15:0];
 Continuous assign for vector nets, addr is a 16 bit vector net
 Addi1 and addit2 are 16-bit vector registers
 assign {cout, sum[3:0]} = a[3:0] + b[3:0] + cin;
 Concatenation
 Left-hand side is a concatenation of a scalar net and a vector net

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Delays
 Delay values control the time between the

change in a right-hand-side operand and
when the new value is assigned to the left-
hand side.
 Regular assignment delay
 Implicit continuous assignment delay
 Net declaration delay

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Implicit Net Declaration
 If a signal name is used to the left of the

continuous assignment, an implicit net
declaration will be inferred for that signal name.
 If the net is connected to a module port, the
width of the inferred net is equal to the width of
the module port.
// Continuous assign. out is a Out was not declared as a wire

net. but an implicit wire declaration for out
wire i1, i2; is done by the simulator
assign out = i1 & i2;

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Regular Assignment Delay
1. When signals in1 and in2 go high at time 20, out goes to a high 10 time units later
(time = 30).
2. When in1 goes low at 60, out changes to low at 70.
3. However, in1 changes to high at 80 but it goes down to low before 10 time units have
elapsed.
4. Hence at the time of recomputation, 10 units after time 80, in1 is 0. Thus, out gets the
value 0. A pulse of width less than the specified assignment delay is not propagated
to the output.
in1
in2
xxxxx
out
time 10 20 30 60 70 80 85

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Implicit Continuous Assignment
Delay
 An equivalent method is to use an implicit
continuous assignment to specify both a
delay and an assignment on the net
//implicit continuous assignment delay

wire #10 out = in1 & in2;
//same as
wire out;
assign #10 out = in1 & in2

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Net Declaration Delay
 A delay can be specified on a net when it is declared without putting a

continuous assignment on the net.
 If a delay is specified on a net out, then any value change applied to the net
out is delayed accordingly. Net declaration delays can also be used in gate-
level modeling.
//Net Delays
wire # 10 out;
assign out = in1 & in2;
//The above statement has the same effect as the following.

wire out;
assign #10 out = in1 & in2;

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Logic Statement Implementation
module multiplexor4_1 (out, in1, in2, in3 ,in4, cntrl1, cntrl2);

output out;
assign out = (in1 & ~cntrl1 & ~cntrl2) |
(in2 & ~cntrl1 & cntrl2) |
(in3 & cntrl1 & ~cntrl2) |
(in4 & cntrl1 & cntrl2);
endmodule

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The Conditional Operator
Syntax Example
conditional_expression ? module multiplexor4_1 (out, in1, in2,
true_expression : in3, in4, cntrl1, cntrl2);
false_expression output out;
assign out = cntrl1 ? (cntrl2 ? in4 : in3)
:(cntrl2 ? in2 : in1);
endmodule

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Overview: Gate Level Modeling
 Verilog
 Basic concept

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Gate Level Modeling
 Identify logic gate primitives provided in

Verilog
 Truth tables for and/or, buf/not and bufif/notif
type gates
 Examples of gate-level designs
 Rise, fall and turn-off delays in the gate-level
design

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Gate Types
 And/Or
 Buf/not
 Bufif/notif
 UDP

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Gate Types: And/Or, Buf/Not Gates
and/or gates buf/not gates

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Gate Types: Examples
 Examples of gate instantiations

wire OUT, IN1, IN2, IN3;
// Basic gate instantiations

and gate1 (OUT, IN1, IN2);
nand gate2 (OUT, IN1, IN2);
or gate3 (OUT, IN1, IN2);
nor gate4 (OUT, IN1, IN2);
xor gate5 (OUT, IN1, IN2);
xnor gate6 (OUT, IN1, IN2);
// More than 2 inputs: 3 input and gate

and gate7 (OUT, IN1, IN2, IN3);
// Gate instantiation without instance name
nand (OUT, IN1, IN2); // This is also a legal instantiation

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Truth Tables for AND/OR Gates
AND 0 1 x z NOR 0 1 x z XOR 0 1 x z
0 0 0 0 0 0 0 1 x x 0 0 1 x x
1 0 1 x x 1 1 1 1 1 1 1 0 x x
x 0 x x x x x 1 X x x x x x x
z 0 x x x z x 1 X X z x x x x

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Truth Tables for AND/OR Gates (2)
NAND 0 1 x z NOR 0 1 x z XNOR 0 1 x z
0 1 1 1 1 0 1 0 x x 0 1 0 x x
1 1 0 x x 1 0 0 0 0 1 0 1 x x
x 1 x x x x x 0 x x x x x x x
z 1 x x x z x 0 x x z x x x x

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Truth Tables for Buf/Not Gates
BUF in out NOT in out

0 0 0 1
1 1 1 0
x x x x
z x z x

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Gate Types: Bufif/Notif Gates
in out in out
control control
bufif1 notif1
in out out
bufif0 control notif0 control

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Gate Types: Examples (2)
 Examples of gate instantiations
wire OUT, IN, CONTROL;
// Basic instantiations of bufif gates

bufif1 b_1 (OUT, IN, CONTROL);
bufif0 b_0 (OUT, IN, CONTROL);
// Basic instantiations of notif gates

notif1 n_1 (OUT, IN, CONTROL);
notif0 n_0 (OUT, IN, CONTROL);

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Truth Tables for Bufif/Notif Gates
control control
BUFIF1 0 1 x z BUFIF0 0 1 x z
0 z 0 L L 0 0 z L L
in 1 z 1 H H in 1 1 z H H
x z x x x x x z x x
z z x x x z x z x x

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Truth Tables for Bufif/Notif Gates (2)
control control
NOTIF1 0 1 x z NOTIF0 0 1 x z
0 z 1 H H 0 1 z H H
in 1 z 0 L L in 1 0 z L L
x z x x x x x z x x
z z x x x z x z x x

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Gate Delays
 Rise delay is associated with a

gate output transition to 1 from
another value.
 Fall delay is associated with a
t_rise
gate output transition to 0 from
another value.
 Turn-off delay is associated
with a gate output transition to
the high impedance value (z)
from another value.
t_fall

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Gate Delays (2)
 Delay specifications
 One delay is specified – its value is used for all
transitions
 Two delays are specified – they refer to rise and fall
delay values respectively
 Three delays are specified – they refer to rise, fall and
turn-off delay values respectively
 Default value is zero

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Gate Delays (3): Example
// Delay is equal to trans_delay for all

transitions
nand #(trans_delay) g1 (out, in1, in2);
// Rise and Fall delays are specified

and #(rise_delay, fall_delay) g2 (out, in1,
in2);
// Rise, Fall and Turn-off delays are specified

bufif0 #(5,7,9) b1 (out, in , control);

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Specify Block Example
module Fullpath(output[2:0] Qbus, output z, input A, B, C, CLOCK);
..........(functionality omitted)...................
specify
specparam tALL=10, tR=20, tF=21;
(A,B,C *>Qbus) = tALL;
(CLOCK *> Qbus) = (tR, tF);
endspecify
endmodule

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UDP
Logic/state Representation/transition Abbreviation
Don’t care (0, 1, or X) ?

Transitions from logic x to logic y (xy).
(xy)
(01), (10), (0x), (1x), (x1), (x0), (?1) ..
Transition from (01) R or r
Transition from (10) R or r
(01), (0X), (X1): positive transition P or p
(10), (1x), (x0): negative transition N or n
Any transition * or (??)
Binary don’t care (0, 1) B or b

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UDP (2)
 Latch with asyncronous reset

//
primitive latch (q, clock, reset, data);
input clock, reset, data;
output q;
reg q;
initial q=1’b1; //initialization
table
// clock reset data q q+
? 1 ? : ? : 1 ;
0 0 0 : ? : 0 ;
1 0 ? : ? : - ;
0 0 1 : ? : 1 ;
endtable
endprimitive

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Ports
 Descriptions
 ports provide the interface by which a module can communicate with its environment
 Types
 input, output or inout (implicitly all are declared as wire in Verilog)
 Port Data Types
 input or inout ports cannot be of type reg, because reg variables store values
 input ports should only reflect the changes of the external signals they are connected to
module DFF (dout,din,clk,resetn);

output dout;
input din,clk,resetn;
reg dout; // As the output of D Flip-Flop holds value it is
declared as reg
always @(posedge clk or negedge resetn)

if (~resetn) dout<=0;
else dout<=din;
endmodule

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Port Connection Rules
 Ports
 Inputs
 Internally, input ports must always be of the type net
 Externally, the inputs can be connected to a variable which is reg or
net
 Outputs
 Internally, output ports can be of the type reg or net
 Externally, the outputs must always be connected to a net
 Inouts
 Internally, inout ports must always be of the type net
 Externally, inout ports must always be connected to a net

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Port Connection Rules (3)
 Connections
 By order
 By name

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Port Connection Rules: By Order
Example
module TOP;
reg data_in,clock,resetn;
wire data_out;
// In the following block DFF module is instantiated and

is called DFF_TEST
// Signals are connected to ports in order
DFF DFF_TEST (data_out,data_in,clock,resetn);
…
<Stimulus>
endmodule

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Port Connection Rules: By Name
 Connecting ports by name

 In large designs where the number of ports is great it may seem
hard to use the ordered method of port connection
 Verilog provides the capability to connect external signals to
ports by the port names
 As long as the port name is not changed the order of ports in the
port list of a module can be rearranged without changing the port
connections in module instantiations
DFF DFF_TEST (.din(data_in), .dout(data_out), .resetn(resetn), .clk(clock));

Lecture - 4
79
Gate Level Implementation of a 4 to
1 Multiplexer
in1
w
in2
x
out
in3
y
in4
z
cntrl1
cntrl2

Lecture - 4
80
Gate Level Implementation of a 4 to
1 Multiplexer: Verilog Description
module multiplexor4_1(out, in1, in2, in3, in4, cntrl1,
cntrl2);
output out;
wire notcntlr1, notcntrl2, w, x, y, z;
not (notcntrl1, cntrl1);
not (notcntrl2, cntrl2);
and (w, in1, notcntrl1, notcntrl2);
and (x, in2, notcntrl1, cntrl2);
and (y, in3, cntrl1, notcntrl2);
and (z, in4, cntrl1, cntrl2);
or (out, w, x, y, z);
endmodule

Lecture - 4
81
Overview: Switch Level Modeling
 Verilog
 Basic concept

Lecture - 4
82
Switch-level Primitives
 MOS switch
 nmos, rnmos, pmos, rpmos, cmos, rcmos
 Bidirectional pass switch
 tran, rtran, tranif1, rtranif1, tranif0, rtranif0
 Switch-level net
 trireg
 Power sources
 pullup, pulldown
Lecture - 4
83
Use of Trireg: Example
pullup(vdd);
trireg (small) #(3,3,10) TriS;
trireg (medium) #(6,7,30) TriM;
trireg (large) #(15,16,50) TriL;
// pass transistor network:

tran (TriM, TriS); // left always wins
tran (TriM, TriL); // right always wins
// NMOS network:
rnmos #1 (TriM, TriS, vdd); // input has no effect
rnmos #1 (TriS, TriL, vdd); // input controls output
rnmos #1 (TriM, TriL, vdd); // connection on output

Lecture - 4
84
Overview: Testbench Creation
 Verilog
 Basic concept

Lecture - 4
85
Initial Block
Syntax Example
Initial begin initial
op1; clock = 1'b0; // variable
op2; initialization
op3;
…. initial
….. begin // multiple
end statements have to be
grouped
alpha = 0;
#10 alpha = 1; //
waveform generation
#20 alpha = 0;
#5 alpha = 1;
#7 alpha = 0;
#10 alpha = 1;
#20 alpha = 0;
end;

Lecture - 4
86
Delay-Based Timing Control
initial begin
a = 0; // executed at simulation time 0
#10 b = 2; // executed at simulation time
10
#15 c = a; // ... at time 25
#b c = 4; // ... at time 27
b=5; // ... at time 27
end

Lecture - 4
87
System Tasks
 Writing to Standard Output

 Keyword: $display, $displayb, $displayh,
$displayo, $write, $writeb, $writeh, $writeo.
 $display("Hello world");
 output: Hello world
 $display($time) // current simulation time.
 output: 460
 $display(" The count is %b", counter);
 output: The count is 0010

Lecture - 4
88
Monitoring a Simulation
 Monitoring and stopping

 Monitoring
 $monitor
 $monitoron
 $monitoroff
 Stopping
 $stop
 $finish

Lecture - 4
89
Looping Constructs
 Looping constructs
 While
 For
 Repeat
 Forever

Lecture - 4
90
Looping Constructs: While Loop
Syntax Example
while (conditional) statement module cup_and_jugs;
integer cup, jug;
initial begin
cup = 0; jug = 0;
while (jug < `JUGVOL)
begin
jug = jug + `CUPVOL;
cup = cup + 1;
end
end
endmodule

Lecture - 4
91
Looping Constructs: For Loop
Syntax Example
for (reg_initialisation ; module initmem;
conditional ; reg_update) reg [15:0] mem16_256 [255:0];
statement reg [15:0] address;
integer index;
initial begin address = 24;
for(index = 0; index < 256;
index = index + 1)
begin mem16_256 [index] = address;
address = address + 1;
$display("%d", mem16_256[index]);
end
end
endmodule
Lecture - 4
92
Looping Constructs: Repeat
Syntax Example
repeat (conditional) statement module comply;
int count;
initial begin
count = 128;
repeat (count) begin
$display("%d seconds to comply", count);
count = count - 1;
end
end
endmodule

Lecture - 4
93
Looping Constructs: Forever Loop
Syntax Example
forever statement reg clock;
initial begin
clock = 1'b0;
forever #5 clock = ~clock;
end
initial #2000 $finish;

Lecture - 4
94
Examples of Gate-Level Designs
 Gate-level design of a 1-bit full adder

module full_adder (sum, cout, a, b, cin);
// port declarations
output sum, cout;
input a, b, cin;
// internal nets
wire n1, n2, n3;
// gate-level netlist
xor g1 (n1, a, b);
and g2 (n2, a, b);
xor g3 (sum, n1, cin);
and g4 (n3, n1, cin);
or g5 (cout, n3, n2);
endmodule

Lecture - 4
95
Examples of Gate-Level Designs (2)
 Design of 4-bit ripple carry full adder using

the module of 1-bit full adder
module fulladder_4bit (sum, cout, a, b, cin);
// port declarations
output [3:0] sum;
Output cout;
Input [3:0] a, b;
input cin;
// internal nets
wire c1, c2, c3;
// Instantiation of 1-bit full adders
full_adder f1 (sum[0], c1, a[0], b[0], cin);
full_adder f2 (sum[1], c2, a[1], b[1], c1);
full_adder f3 (sum[2], c3, a[2], b[2], c2);
full_adder f4 (sum[3], cout, a[3], b[3], c3);
endmodule

Lecture - 4
96
Testbench for a 4-bit Ripple Carry
Full Adder
module TEST;
// variables
reg [3:0] A, B;
reg CIN;
wire [3:0] SUM;
wire cout;
// instantiate the 4-bit ripple carry full adder and
call it ADDER_TEST
fulladder_4bit ADDER_TEST (SUM, COUT, A, B, CIN);
// signal monitoring
Initial
begin
$monitor ($time, “ A= %b, B= %b, CIN= %b, SUM=%b,
COUT=%b\n”, A, B, CIN, SUM, COUT);
end

Lecture - 4
97
Testbench for a 4-bit Ripple Carry
Full Adder (2)
// input signals
initial
0 A= 0000, B= 0000, CIN= 0, SUM=0000, COUT=0
begin
A=4’d0; B=4’d0; CIN=1’b0; 5 A= 0011, B= 0100, CIN= 0, SUM=0111, COUT=0
VCS
#5 A=4’d3; B=4’d4; 10 A= 0010, B= 0101, CIN= 0,SUM=0111,COUT=0
Simulation
#5 A=4’d10; B=4’d15;
#5 A=4’d10; B=4’d5; CIN=1’b1; 25 A= 1010, B= 0101, CIN= 1,SUM=0000,COUT=1
end
endmodule

Lecture - 4
98
VCS Simulation Results for a 4-bit
Ripple Carry Full Adder

Lecture - 4
99
VCD File Ragment
$scope module AAA_tmax_testbench_1_16 $end

.............
$var wire 1 > C405APUDCDINSTRUCTION04 $end
$var wire 1 ? C405APUDCDINSTRUCTION05 $end
$var wire 1 @ C405APUDCDINSTRUCTION06 $end
$var wire 1 A C405APUDCDINSTRUCTION07 $end
..............
#30
0#
#40
0$
.........

Lecture - 4
100
The Twelve Verilog Timing Checks
Clock-Clock Clock-Data Clock-control

Data Che
Checks Checks Checks
$skew $setup $recovery

$width
$timeskew $hold $removal
$period
$fullskew $setuphold* $recrem*
$nochange

Lecture - 4
101
Overview: Tasks and Functions
 Verilog
 Basic concept

Lecture - 4
102
Tasks and Functions
 Tasks
 Can be addressed by means of hierarchical names
 Included in design hierarchy
 Arguments
 Output
 Inout
 Input
 Functions
 Can be addressed by means of hierarchical names
 Included in design hierarchy
 Arguments
 Input

Lecture - 4
103
Differences Between Tasks and
Functions
 Functions  Tasks
 A function can enable another  A task can enable other tasks and
function but not another task functions
 Functions always execute in 0  Tasks may execute in non-zero
simulation time simulation time
 Functions must not contain any  Tasks may contain delay, event, or
delay, event or timing control timing control statements
statements  Tasks may have zero or more
 Functions must have at least one arguments of type input, output or
input argument. They can have inout
more than one input  Tasks do not return with a value
 Functions always return a single but can pass multiple values
value. They cannot have output or through output and inout
inout arguments arguments

Lecture - 4
104
Tasks
 Keywords – task and endtask

 Use tasks if any of these conditions is true
 There are delay, timing or event control constructs in the procedure
 The procedure has zero or more than one output arguments
 The procedure has no input arguments
task bitwise_oper; // A and B are input arguments to the task

output [15:0] ab_and, ab_or, ab_xor; // Somewhere in module
input [15:0] a,b; bitwise_oper (AB_AND, AB_OR, AB_XOR, A, B);
Begin
#10 ab_and = a & b;
ab_or = a | b;
ab_xor = a ^ b;
End
endtask task invocation

Lecture - 4
105
Functions
 Keywords – function and endfunction

 Use functions if all of these conditions are true
 There are no delay, timing or event control constructs in the procedure
 The procedure returns a single value
 There is at least one input argument
function calc_parity; // addr is an input to the function
input [31:0] address; // Somewhere in module
begin parity = calc_parity(addr);
calc_parity = ^ address
end
Endfunction function invocation

Lecture - 4
106
Summary
 Tasks and functions are used to define common Verilog functionality that is
used in many places in the design.
 Tasks can take any number of input, inout or output arguments. Delay,
event or timing control constructs are permitted in tasks. Tasks can enable
other tasks and functions.
 Functions are used when exactly one return value is required and at least
one input argument is specified. Delay, event or timing control constructs
are not permitted in functions. Functions can invoke other functions but
cannot invoke other tasks.
 Tasks and functions are included in a design hierarchy and can be
addressed by hierarchical name referencing.
 A register with name as the function name is declared implicitly when a
function is declared. The return value of the function is passed back in this
register.
Lecture - 4
107
Lecture - 4
108

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Professor: Sci.D., Professor

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 The Role and Classification of HDLs

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Traditional header format Newer header format

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wire a1; // wire is a keyword, a1 is an identifier

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 Sized numbers <size>`<base

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 Underscore, Question mark

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Name Keyword Default value Default size

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Name Keyword Default value Default size

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 Wire or register which is more than 1 bit in

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reg data [7:0]; // 8 1-bit data elements

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 Statements in a parallel block are executed

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 Syntax: `<keyword> Example:

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 Definition of blocking and non-blocking procedural assignments

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 Update values of reg, integer, real, or time

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#15 reg_a[2] = 1'b1;

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reg_a[2] <= #15 1'b1;

reg_b[15:13] <= #10 {x, y, z};

count <= count + 1;

end Synopsys University Courseware

module multiplexor4_1 (out, in1, in2, in3 ,in4, cntrl1,

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module multiplexor4_1 (out, in1, in2, in3, in4, cntrl1, cntrl2);

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