System Design on Zynq using Vivado

Zynq
Vivado 2015.2 Version

This material exempt per Department of Commerce license exception TSU © Copyright 2015 Xilinx
Course Objectives

After completing this course, you will be able to:

– Describe general FPGA architectures

– Understand the Vivado design flow
– Create and apply I/O and timing constraints
– Rapidly architect an embedded system targeting the AXI4 interface standard using Vivado and IP
Integrator
– Extend the system by adding peripherals
• Create and add a custom peripheral using IP Integrator

Course Intro 01- 2 © Copyright 2015 Xilinx

Course Objectives

– Create and debug software applications

– Apply advanced debugging techniques, including the use of the Vivado Logic Analyzer for debugging
an embedded system
– Profile software application and observe impact of porting a software function into an hardware
accelerator
– Describe the high level synthesis flow
– Perform system-level integration of blocks generated by the Vivado HLS tool

Course Intro 01- 3 © Copyright 2015 Xilinx

Course Outline
Day 1

The course consists of the following modules:

7-Series Architecture Overview
Vivado Design Flow
Lab 1: Vivado Design Flow
Xilinx Design Constraints
Lab 2: Xilinx Design Constraints
IP Integrator and Embedded System Design Flow
Lab 3: Create a Processor System using IP Integrator

Course Intro 01- 4 © Copyright 2015 Xilinx

Course Outline
Day 2

Creating and Adding Your Own Peripheral in an Embedded System

Lab 4: Creating and Adding Custom IP
System Debugging using Vivado Logic Analyzer and SDK
Lab 5: Debugging using Vivado Logic Analyzer
Profiling and Performance Improvement
Introduction to High-Level Synthesis (HLS)
Improving Performance and Resource Utilization
Creating an Hardware Accelerator
Lab 6: Creating a Processor System to filter Audio Signal

Course Intro 01- 5 © Copyright 2015 Xilinx

Prerequisites

Basic HDL knowledge (VHDL or Verilog)

Digital design knowledge and experience
Basic understanding of C programming

Course Intro 01- 6 © Copyright 2015 Xilinx

Platform Support

Vivado System Design Suite 2015.2

Xilinx University boards
– ZedBoard, Zybo
Supported Operating Systems
– Windows 7 SP1 Professional (64 Bit)
– Windows 8.1 Professional (64 Bit)
– Red Hat Enterprise Linux 6.5 – 6.6 (64 Bit)
– Red Hat Enterprise Linux 7.0 (64 Bit)
– SUSE Linux Enterprise 12.0 (64 Bit)
– Centos Linux 7.0 (64 Bit)
– Ubuntu Linux 14.04 LTS (64 Bit)
Refer to UG973 for release notes, installation, and Licensing

Course Intro 01- 7 © Copyright 2015 Xilinx