Lab3 Intro

Create a Processor System using IP

Integrator

Zynq
Vivado 2015.2 Version

This material exempt per Department of Commerce license exception TSU © Copyright 2015 Xilinx
Introduction

This lab guides you through the process of using Vivado and IP Integrator to create a
simple ARM Cortex-A9 based processor design targeting either the ZedBoard or the
Zybo board. You will use IP Integrator to create the hardware block diagram and XSDK
to create an example application to verify the hardware functionality.

Lab3 Intro 14a- 2 © Copyright 2015 Xilinx

ARM Cortex-A9 based Embedded System Design

DDR3
Memory Memory
Controller

RS232 UART
PL
ARM
Cortex-A9

AXI3 AXI
M_AXI_GP0 Interconnect AXI4-Lite
GPIO Push-Buttons
Block
AXI4-Lite
PS GPIO DIP Switches

Lab3 Intro 14a- 3 © Copyright 2015 Xilinx

Procedure

Create a project using Vivado

Create the system using IP Integrator from Vivado and build basic system
Add two instances of GPIO
Make GPIO connections external
Generate bitstream and Export to SDK
Generate TestApp application in SDK
Verify the functionality in hardware using the target board

Lab3 Intro 14a- 4 © Copyright 2015 Xilinx

Summary

Vivado and the IP Integrator allow base embedded processor systems and applications
to be generated very quickly. GPIO peripherals were added from the IP catalog and
connected to the Processing System through the 32b Master GP0 interface. The
peripherals were configured and external FPGA connections were established. Pin
location constraints, since we used the board aware port names, were automatically
applied to connect the peripherals to the push buttons and DIP switches of the target
board. After the system has been defined, the hardware can be exported and SDK can
be invoked from Vivado. Software development was done in XSDK which provides
several application templates including memory tests. You verified the operation of the
hardware by downloading a test application, executing on the processor, and observing
the output in the serial terminal window.

Lab3 Intro 14a- 5 © Copyright 2015 Xilinx