Lab5 Intro

System Debugging Using Vivado Logic

Analyzer and SDK

Zynq
Vivado 2015.2 Version

This material exempt per Department of Commerce license exception TSU © Copyright 2015 Xilinx
Introduction

Software and hardware interacts with each other in an embedded system. The Xilinx
SDK includes both GNU and the Xilinx Microprocessor Debugger (XMD) as software
debugging tools. The Vivado hardware logic analyzer tool allows for hardware
debugging by providing access to the internal signals, using number of cores, without
necessarily bringing them out via the package pins. These powerful cores may reside in
the programmable logic (PL) portion of the device and can be configured with several
modes that can monitor signals within the design. Vivado provides capabilities of
marking any net at several stages of the design flow. In this lab you will be introduced
to various debugging cores. Vivado and XSDK includes cross-triggering capability
which allows software exception (breakpoint) to trigger logic analyzer, and hardware
condition detected by the logic analyzer stops software execution

Lab5 Intro 22a- 2 © Copyright 2015 Xilinx

ARM Cortex-A9 based Embedded System Design
Debugging using Hardware Logic Analyzer Cores and Mark
Debug

DDR3
PL
Memory Memory
Controller TRIGGER_IN
TRIGGER_OUT

RS232 UART Mark Debug VIO ILA

ARM
AXI4-Lite
Cortex-A9 MATH_IP

AXI4-Lite
LED_IP LEDs
AXI3 AXI
M_AXI_GP0 Interconnect AXI4-Lite
Block GPIO Switches

AXI4-Lite
GPIO Push Buttons

PS

Lab5 Intro 22a- 3 © Copyright 2015 Xilinx

The Custom IP – MATH_IP

clk reset_n
sel

ain
slv_reg0
ain_vio
bin + result
slv_reg1
bin_vio

Lab5 Intro 22a- 4 © Copyright 2015 Xilinx

Procedure

Open lab4 Vivado project and save as lab5

Add the provided custom IP
Enable cross triggering and add the VIO and ILA cores
Synthesize the design and assign the S_AXI nets for debugging
Generate the bitstream
Generate the application in the XSDK
Test and debug in design using the target board

Lab5 Intro 22a- 5 © Copyright 2015 Xilinx

Summary

In this lab, you added a custom core with extra ports so you can debug the design
using the VIO core. You instantiated the ILA and the VIO cores into the design. You used
Mark Debug feature of Vivado to debug the AXI transactions on the custom peripheral.
You then opened the hardware session from Vivado, setup various cores, and verified
the design and core functionality, including cross-triggering, using XSDK and the
Vivado logic analyzer.

Lab5 Intro 22a- 6 © Copyright 2015 Xilinx