VLSI Technology

Dr Pushpa Giri
Asst. Prof., ECE dept.
The RCA clean is a standard set of wafer cleaning steps which need to be
performed before high-temperature processing steps (oxidation, diffusion,
CVD) of silicon wafers in semiconductor manufacturing.

Werner Kern developed the basic procedure in 1965 while working for RCA,
the Radio Corporation of America. It involves the following chemical
processes performed in sequence:

1.Removal of the organic contaminants (organic clean + particle clean)

2.Removal of thin oxide layer (oxide strip, optional)
3.Removal of ionic contamination (ionic clean)
First step (RCA-1): organic clean + particle clean
The first step (called SC-1, where SC stands for Standard Clean) is performed with a solution of (ratios may vary) [2]
• 5 parts of deionized water
• 1 part of ammonia water, (29% by weight of NH3)
• 1 part of aqueous H2O2 (hydrogen peroxide, 30%)
at 75 or 80 °C typically for 10 minutes. This base-peroxide mixture removes organic residues. Particles are also
very effectively removed, even insoluble particles, since RCA-1 modifies the surface and particle zeta
potentials and causes them to repel. This treatment results in the formation of a thin silicon dioxide layer (about 10
Angstrom) on the silicon surface, along with a certain degree of metallic contamination (notably iron) that will be
removed in subsequent steps.

Second step (optional): oxide strip

The optional second step (for bare silicon wafers) is a short immersion in a 1:100 or 1:50 solution of aqueous HF
(hydrofluoric acid) at 25 °C for about fifteen seconds, in order to remove the thin oxide layer and some fraction of
ionic contaminants. If this step is performed without ultra high purity materials and ultra clean containers, it can
lead to recontamination since the bare silicon surface is very reactive. In any case, the subsequent step (RCA-2)
dissolves and regrows the oxide layer.
Third step (RCA-2): ionic clean
The third and last step (called SC-2) is performed with a solution of (ratios may vary)
• 6 parts of deionized water
• 1 part of aqueous HCl (hydrochloric acid, 37% by weight)
• 1 part of aqueous H2O2 (hydrogen peroxide, 30%)
at 75 or 80 °C, typically for 10 minutes. This treatment effectively removes the remaining traces of metallic (ionic)
contaminants, some of which were introduced in the RCA-1 cleaning step. It also leaves a thin passivating layer on the
wafer surface, which protects the surface from subsequent contamination (bare exposed silicon is contaminated
immediately).

Fourth step: rinsing and drying

Provided the RCA clean is performed with high-purity chemicals and clean glassware, it results in a very clean wafer
surface while the wafer is still submersed in water. The rinsing and drying steps must be performed correctly (e.g., with
flowing water) since the surface can be easily recontaminated by organics and particulates floating on the surface of
water.

A variety of procedures can be used to rinse and dry the wafer effectively.
Clean Room
 Si Ge
Low Junction Leakage Current High Junction Leakage Current
Wide Bandgap (1.1 eV) Narrow Bandgap (.66 eV)
Operate up to 150oC Operate up to 100oC
Thermally grown SiO2 NA
230 kΩcm 47 Ωcm
Economy Costly
 Electronic-Grade Silicon
• Step I:
SiC(s) + SiO2(s)= Si (l) + SiO(g) + CO(g)

• Step II:
Si (s) +3HCl(g) = SiHCl3(g) + H2(g)
+Heat
• Production of EGS using CVD reactor
2SiHCl3(g) + 2H2(g) = 2Si(s) + 6HCL(g)

• Production of EGS from silane

SiH4 (g) + Heat = Si(s) + 2H2(g)
Bridgman method
 • The methods involve heating polycrystalline
material above its melting point and slowly cooling
Bridgman method it from one end of its container, where a seed
crystal is located.
• A single crystal of the same crystallographic
orientation as the seed material is grown on the seed
and is progressively formed along the length of the
container.
• The process can be carried out in a horizontal or
vertical orientation, and usually involves a rotating
crucible/ampoule to stir the melt.
• The Bridgman method is a popular way of producing
certain semiconductor crystals such as gallium
arsenide, for which the Czochralski method is more
difficult.
• The process can reliably produce single crystal
ingots, but does not necessarily result in uniform
properties through the crystal.
 Moore’s Law
 1965: Gordon Moore plotted transistor on each chip
 Fit straight line on semilog scale
 Transistor counts have doubled every 26 months
1,000,000,000

100,000,000
Integration Levels
Pentium 4
Pentium III
10,000,000 Pentium II
Pentium Pro SSI: 10 gates
Transistors

Pentium
Intel486
1,000,000

MSI: 1000 gates

Intel386
80286
100,000
8086
10,000 8080

1,000
4004
8008
LSI: 10,000 gates
1970 1975 1980 1985 1990 1995 2000 VLSI: > 20k gates
Year
Scaling of MOS Circuits

ECE
 Scaling
VLSI technology is constantly evolving towards smaller
line widths
Reduced feature size generally leads to
better / faster performance
More gate / chip
More accurate description of modern technology is ULSI
(ultra large scale integration

ECE
 Scaling Factors
In our discussions we will consider 2 scaling factors, α and
β
1/ β is the scaling factor for VDD and oxide thickness D
1/ α is scaling factor for all other linear dimensions
We will assume electric field is kept constant

ECE
 Scaling Factors for Device Parameters
Simple derivations showing the effects of scaling are derived in Pucknell and Eshraghian
pages 125 - 129
It is important that you understand how the following parameters are effected by scaling
Gate Area
Gate Capacitance per unit area
Gate Capacitance
Charge in Channel
Channel Resistance
Transistor Delay
Maximum Operating Frequency
Transistor Current
Switching Energy
Power Dissipation Per Gate (Static and Dynamic)
Power Dissipation Per Unit Area
Power - Speed Product

ECE
Scaling of Interconnects
Resistance of track R ~ L / wt A
R (scaled) ~ (L / α) / ( (w/ α )* (t
/α))
t w L
R(scaled) = αR
therefore resistance increases with
scaling

ECE
 Scaling - Time Constant
Time constant of track connected to gate,
T = R * Cg
T(scaled) = α R * (β / α2) *Cg = (β / α) *R*Cg
Let β = α, therefore T is unscaled!
Therefore delays in tracks don’t reduce with scaling
Therefore as tracks get proportionately larger, effect gets worse
Cross talk between connections gets worse because of reduced spacing

ECE
NMOS Fabrication
NMOS Fabrication
 Ion implantation
• Ion implantation is a low-temperature process by which ions of one element are
accelerated into a solid target, thereby changing the physical, chemical, or electrical
properties of the target.
• Ion implantation is used in semiconductor device fabrication and in metal finishing,
as well as in materials science research.
• The ions can alter the elemental composition of the target (if the ions differ in
composition from the target) if they stop and remain in the target. Ion implantation
also causes chemical and physical changes when the ions impinge on the target at
high energy.
• The crystal structure of the target can be damaged or even destroyed by the
energetic collision cascades, and ions of sufficiently high energy (10s of MeV) can
cause nuclear transmutation.
 Diffusion Process
In the diffusion process, the dopant atoms are introduced from the gas phase of by
using doped-oxide sources. The doping concentration decreases monotonically from
the surface, and the in-depth distribution of the dopant is determined mainly by the
temperature and diffusion time.
 Planar Process
• The Planar Process is a manufacturing process used in the semiconductor industry to build individual
components of a transistor, and in turn, connect those transistors together.

• It is the primary process by which silicon integrated circuit chips are built. The process utilizes
the surface passivation and thermal oxidation methods.

• The planar process was developed at Fairchild Semiconductor in 1959.

• The key concept is to view a circuit in its two-dimensional projection (a plane), thus
allowing the use of photographic processing concepts such as film negatives to mask the
projection of light exposed chemicals.

• This allows the use of a series of exposures on a substrate (silicon) to create silicon
oxide (insulators) or doped regions (conductors). Together with the use of metallization,
and the concepts of p–n junction isolation and surface passivation, it is possible to create
circuits on a single silicon crystal slice (a wafer) from a monocrystalline silicon boule.

• The process involves the basic procedures of silicon dioxide (SiO2) oxidation,
SiO2 etching and heat diffusion. The final steps involves oxidizing the entire wafer with an
SiO2 layer, etching contact vias to the transistors, and depositing a covering metal layer
over the oxide, thus connecting the transistors without manually wiring them together.
At a 1958 Electrochemical Society meeting, Mohamed Atalla presented a paper about the surface passivation of
PN junctions by thermal oxidation, based on his 1957 BTL memos.
Swiss engineer Jean Hoerni attended the same 1958 meeting, and was intrigued by Atalla's presentation. Hoerni
came up with the "planar idea" one morning while thinking about Atalla's device. Taking advantage of silicon
dioxide's passivating effect on the silicon surface, Hoerni proposed to make transistors that were protected by a
layer of silicon dioxide. This led to the first successful product implementation of the Atalla silicon transistor
passivation technique by thermal oxide.
The planar process was developed by Jean Hoern, one of the "traitorous eight", while working at Fairchild
Semiconductor, with a first patent issued 1959.
Together with the use of metallization (to join together the integrated circuits), and the concept of p–n junction
isolation (from Kurt Lehovec), the researchers at Fairchild were able to create circuits on a single silicon crystal
slice (a wafer) from a monocrystalline silicon boule.
In 1959, Robert Noyce built on Hoerni's work with his conception of an integrated circuit (IC), which added a
layer of metal to the top of Hoerni's basic structure to connect different components, such as
transistors, capacitors, or resistors, located on the same piece of silicon. The planar process provided a powerful
way of implementing an integrated circuit that was superior to earlier conceptions of the integrated
circuit. Noyce's invention was the first monolithic IC chip.
Early versions of the planar process used a photolithography process using near-ultraviolet light from a mercury
vapor lamp. As of 2011, small features are typically made with 193 nm "deep" UV lithography. Some
researchers use even higher-energy extreme ultraviolet lithography.
 Alloy-Junction
• The germanium alloy-junction transistor, or alloy transistor, was an early type of bipolar junction
transistor, developed at General Electric and RCA in 1951 as an improvement over the earlier grown-
junction transistor.
• The usual construction of an alloy-junction transistor is a germanium crystal forming the base, with emitter
and collector alloy beads fused on opposite sides.
• Indium and antimony were commonly used to form the alloy junctions on a bar of N-type germanium.
• The collector junction pellet would be about 50 mils (thousandths of an inch) in diameter, and the emitter
pellet about 20 mils.
• The base region would be on the order of 1 mil (0.001 inches, 25 μm) thick. All types of alloy-junction
transistors became obsolete in the early 1960s, with the introduction of the planar transistor which could be
mass-produced easily while alloy-junction transistors had to be made individually.
• The first germanium planar transistors had much worse characteristics than alloy-junction germanium
transistors of the period, but they cost much less, and the characteristics of planar transistors improved very
rapidly, quickly exceeding those of all earlier germanium transistors.
 Micro-alloy transistor

• The micro-alloy transistor (MAT) was developed by Philco as an improved

type of alloy-junction transistor, it offered much higher speed.

• It is constructed of a semiconductor crystal forming the base, into which a pair

of wells are etched (similar to Philco's earlier surface-barrier transistor) on
opposite sides then fusing emitter and collector alloy beads into the wells.
 Micro-alloy diffused transistor

• The micro-alloy diffused transistor (MADT), or micro-alloy diffused-base transistor, was developed
by Philco as an improved type of micro-alloy transistor; it offered even higher speed. It is a type
of diffused-base transistor.

• Before using electrochemical techniques and etching depression wells into the base semiconductor
crystal material, a heated diffused phosphorus gaseous layer is created over the entire intrinsic
semiconductor base crystal, creating a N-type graded base semiconductor material. The emitter well is
etched very shallow into this diffused base layer.

• For high-speed operation, the collector well is etched all the way through the diffused base layer and
through most of the intrinsic base semiconductor region, forming an extremely thin base
region. A doping-engineered electric field was created in the diffused base layer to reduce the charge
carrier base transit time (similar to the drift-field transistor).
 Post-alloy diffused transistor

• The post-alloy diffused transistor (PADT), or post-alloy diffused-base transistor, was developed
by Philips (but GE and RCA filed for patent and Jacques Pankove of RCA received patent for it) as an
improvement to the germanium alloy-junction transistor, it offered even higher speed. It is a type of diffused-
base transistor.

• The Philco micro-alloy diffused transistor had a mechanical weakness that ultimately limited their speed; the
thin diffused base layer would break if made too thin, but to get high speed it needed to be as thin as possible.
Also it was very hard to control alloying on both sides of such a thin layer.

• The post-alloy diffused transistor solved this problem by making the bulk semiconductor crystal the collector
(instead of the base), which could be as thick as necessary for mechanical strength. The diffused base layer was
created on top of this. Then two alloy beads, one P-type and one N-type were fused on top of the diffused base
layer. The bead having the same type as the base dopant then became part of the base and the bead having the
opposite type from the base dopant became the emitter.

• A doping-engineered electric field was created in the diffused base layer to reduce the charge carrier base transit
time (similar to the drift-field transistor).
 (a) (b) (c)

(d) (e) (f)

(a) TG 51 PNP germanium alloy transistor Made by TEWA Poland (b) TG 51 PNP germanium alloy transistor Made by TEWA Poland
(c) General Electric 2N1307 PNP germanium alloy transistor (d) General Electric 2N1307 PNP germanium alloy transistor (e) RCA
2N404 Germanium PNP Transistor Medium Speed Switch (f) PNP germanium alloy transistor intended as AF amplifier / switch
UNIT II
 Si Ge
Low Junction Leakage Current High Junction Leakage Current
Wide Bandgap (1.1 eV) Narrow Bandgap (.66 eV)
Operate up to 150oC Operate up to 100oC
Thermally grown SiO2 NA
230 kΩcm 47 Ωcm
Economy Costly
 Electronic-Grade Silicon
• Step I:
SiC(s) + SiO2(s)= Si (l) + SiO(g) + CO(g)

• Step II:
Si (s) +3HCl(g) = SiHCl3(g) + H2(g)
+Heat
• Production of EGS using CVD reactor
2SiHCl3(g) + 2H2(g) = 2Si(s) + 6HCL(g)

• Production of EGS from silane

SiH4 (g) + Heat = Si(s) + 2H2(g)
Bridgman method
 • The methods involve heating polycrystalline
material above its melting point and slowly cooling
Bridgman method it from one end of its container, where a seed
crystal is located.
• A single crystal of the same crystallographic
orientation as the seed material is grown on the seed
and is progressively formed along the length of the
container.
• The process can be carried out in a horizontal or
vertical orientation, and usually involves a rotating
crucible/ampoule to stir the melt.
• The Bridgman method is a popular way of producing
certain semiconductor crystals such as gallium
arsenide, for which the Czochralski method is more
difficult.
• The process can reliably produce single crystal
ingots, but does not necessarily result in uniform
properties through the crystal.
 Characterization Techniques for nanostructures
X-ray diffraction (XRD) is an analytical tool mainly employed for the identification of a geometrical
structure, orientation, average crystalline size and strain in the films.
The basic law that governs the diffraction method is the Bragg’s law. According to this law, when a
monochromatic X-ray impinges upon the atoms in a crystal lattice, each atom acts as a source of scattering.
Thus, the crystal lattice acts as a series of parallel reflecting planes and the intensity of the reflected beam
will be maximum at certain angles when the path difference between two reflected waves from two different
planes is an integral multiple of the operating wavelength “λ”.
2d sinθ=nλ
where n is the order of diffraction, λ is the wavelength of the X-rays, d is the spacing between consecutive
parallel planes and θ is the glancing angle.

Figure 8: Schematic diagram for working principal of XRD pattern [8]

 Scanning Electron Microscopy (SEM)
SEM is a kind of microscope used to magnify samples
on a nano-scale.
It uses a highly energetic electron beam to scan the
sample and produce an extremely magnified image.
The development of image of the sample’s surface in
the SEM takes place very precisely point by point
scanning with high-energy electrons beam in a raster
scan order.
The electrons come in a contact with the atoms of the
sample and generate variety of signals carrying the
information about the morphology of the surface,
composition and the electrical conductivity of the
sample.
Generally an electron beam is thermionically ejected
from an electron gun attached with a tungsten filament
cathode. Figure 9: The schematic diagram of SEM [9]
The resolution of SEM can be reached up to 200nm.
 Energy dispersive X-ray (EDX) or (EDS)

(EDX) or (EDS) is an analytical technique used to extract the

information about a specimen composition from its X-ray emission.
For this purpose, an EDX detector is installed as an integrated part of
SEM. Thus employing the scanning ability of the SEM, it is possible
to form an elemental composition map.
When an electron from an outer atomic shell falls into an inner shell
vacancy, the X-rays are emitted by the interaction between a charged
beam and an electron in the shell. Thus, the X-ray energy is
determined by the energy difference between these two shells, which
is unique for each element. The energy of the X-rays emitted from a
specimen can be measured by EDX. Figure 10: Schematic diagram of Energy
An EDX graph is normally represented as X-ray counts as a function Dispersive X-ray spectroscopy [10]

of its energy in keV.

Elements can be identified from the graph by their narrow peaks at
the given energies.
 Atomic Force Microscopy (AFM)

AFM is a high-resolution microscopy technique which produces

precise topographic images of a sample by scanning the surface
with a nanometer-scale probe.
An AFM image is produced by exploring the interaction between
the AFM tip and the scanned surface. Also, being capable to
move in the three spatial dimensions, the AFM system can
produce a three dimensional (3D) image with accuracy in the sub-
nanometer range. It is operated by measuring the force between a
probe and the sample.
The probe has a sharp tip, which is a 3-6 μm tall pyramid with
15-40 μm end radius.
The AFM consists of three main parts: (1) a cantilever and a tip,
the probe of the system (2) a piezoelectric transducer to control
the cantilever movements in x, y and z direction; and (3) a laser
and a detector to detect the cantilever deflection due to the
Figure 11: Schematic diagram on working principal
interaction of the AFM tip with the scanned surface. of atomic force microscope [11]
 Ellipsometric

Ellipsometric is an optical technique for investigating

the dielectric properties, composition, thickness, optical
constant and roughness of the thin films.
Ellipsometry uses the fact that light undergoes some change in
polarization when it is reflected off the surface of a material.
The polarization change is characteristic of the surface
structure of the sample and so we can obtain various
information about the material simply by analyzing the
reflected light beam.

Advantages
Non-destructive and non-contact technique Figure12: Schematic setup of an ellipsometry
experiment [12]
No sample preparation
Solid and liquid samples
Fast thin film thickness mapping
Single and multi layer samples
Accurate measurement of ultra-thin films of thickness < 10nm