High Voltage

Engineering
Prepared by: Dr/ Shaymaa Ahmed
Lec: 2
 Full-wave rectifier circuit
• A full-wave rectifier circuit is shown in next Fig. In the positive half cycle, the
diode D1 conducts and charges the capacitor C, while in the negative half cycle
diode D2 conducts and charges the capacitor C. Therefore, each diode is conducting
for one half-cycle with a time delay of T/2. The transformer requires a center tapped
secondary with a rating of 2V.
• The maximum voltage produced in this rectifier circuit is approximately equal to
half the peak value of the ac voltage of the HV transformer secondary.
• Thus single-phase full-wave rectifier circuits can be used for HV applications only
if the high tension winding of the transformer is earthed at its midpoint and if the dc
output is single-ended grounded.
• The supply input voltage (sinusoidal) and the output voltages of both the half-wave
and full-wave rectifier circuits are given in Fig. for the purpose of comparison.
Fig. Full-wave rectifier circuit using center-tapped transformer.
 Fig. Input and output waveforms of half and full wave rectifiers Input sine wave, b) output with half-wave rectifier and
condenser c) Output with full-wave rectifier, d) Vmax, Vmean, and ripple voltage dV with condenser of a full wave rectifier.
• Both the half-wave and full-wave rectifier circuits produce dc voltages less than the
ac maximum voltage.
• Also, ripple voltage or voltage fluctuations are present. This ripple voltage δV is
larger for half-wave rectifier than that for a full-wave rectifier, since the discharge
period in the case of half wave rectifier is larger as shown in Fig. b or Fig.b.
• It should be mentioned that the ripple voltage δV depends on:
• (a)The supply voltage frequency f.
• (b)The time constant RLC.
• (c) The reactance of the supply transformer XL.
• For half-wave rectifiers, the ripple frequency is equal to the supply frequency and
for full-wave rectifiers, it is twice that value. The ripple voltage is to be kept as low
as possible or within a reasonable limit with the proper choice of the output filter.
Approximate value of smoothing capacitor
• With n pulses per second, the time interval between voltage peaks = 1/n sec.
• This is nearly equal to the capacitor discharge time for small values of ripple
voltage. Let the main dc load current = Idc A.
• The charge of the capacitor QC is given by:
• QC = capacitance in Farads x voltage change
• = C ∆V Coulombs.
• The charge of the capacitor QC is also given by:
• QC = Idc x t
• where Idc = current in amperes and t = time in seconds.
• The charge given to load = charge lost by capacitor between charging pulses.
• Hence, the design value of the capacitance can be calculated for a certain dc output current
(Idc) and a certain amount of ripple voltage (DV).
• Example 2.5
• Estimate the size of a suitable smoothing capacitor for the following duty when a full-wave
rectifier is used; Vdc = 400 kV, ripple voltage = 3% of Vdc, load resistance = 5000 kW,
frequency = 50 Hz.
• Solution
• Voltage is changing from 400 kV + 3% to 400 kV – 3%
• i.e., from 412 kV to 388 kV.
• Hence DV = 24 kV.
Example 2.6
A load is to be supplied with 50 mA at a mean voltage of 285 kV using a full-wave
rectifier. The peak value of the ac supply is 300 kV and the frequency is 50 Hz. Calculate
the approximate size of a suitablesmoothing capacitor.
Solution

/
Discharge during this period = Idc x time = 50 x 10-3 x 0.01 = 0.5 x 10-3 C
Mean dc voltage = 285 kV
Peak voltage = 300 kV
Change in voltage from mean to maximum = 15 kV.
By symmetry, the change from mean to minimum voltage is = 15 kV.Total (peak-to-peak)
voltage = 30 kV.

 C 3 0 1 0 3   0 .5 1 0 3
0.5𝑥10−3
𝐶= 3
= 16.67𝑥10−9 𝐹 = 16.67 𝑛𝐹
30𝑥10
Voltage doubler circuits
a. Voltage multiplier circuits
b. Cascaded circuits

• A. Voltage multiplier circuits

• 1. single phase voltage doubler
 In voltage doubler circuit, shown in previous Fig., capacitor C 1 is charged through diode D1 to a voltage of +Vmax
with polarity as shown in the figure during the negative half cycle.

 As the voltage of the transformer rises to positive V max during the negative half cycle, the potential of the other

terminal of C1 rises to a voltage of 2Vmax. Thus, the condenser C2 in turn is charged through D2 to 2Vmax.

 Normally the dc output voltage on load will be less than 2V max, depending on the time constant C2RL and the
forward charging time constants.

 The ripple voltage of this circuit will be about 2% for R L/r≤10and X/r≤0.25, where X and r are the reactance and
resistance of the input transformer, respectively.

 The diodes are rated to a peak inverse voltage of 2V max, and the condensers C1 and C2 must also have the same
rating. If the load current is large, the ripple is also more.

 Cascaded voltage doublers are used when larger output voltages are needed without changing the input
transformer voltage level.
Cockcroft-Walton voltage multiplier circuit
 The voltage multiplier circuit using the Cockcroft-Walton principle is shown in Fig. 2.19. The first stage, i.e.,
D1, D2, C1, C2, and the transformer T are identical to those in the voltage doubler shown in Fig. 2.18 before.

 For higher output voltages of 4, 6, 2n of the input voltage V (where n is an integer number), the circuit is
repeated with cascade or series connection.

 The whole circuit is a cascade arrangement and points d, c, b and a are successively raised to potentials of
2V, 4V, 6V and 8V.

 The use of several stages arranged in this manner enable very high voltages to be obtained.

 Each capacitor and rectifier has to withstand only twice the transformer voltage irrespective of the output
voltage of the whole unit.

 With load, the output voltage of the cascaded rectifiers is less than 2nV max, where n is the number of stages.
Principle of operation (no load operation)
• 1. During –ve half cycle C1 charged to Vmax through D1.
• 2. During +ve half cycle C2 charged to Vmax through D2.
• 3. For the next –ve half cycle
• C1: charged to Vmax
• Point A: has zero voltage
• Point B: has 2Vmax
• Point C: has now zero voltage
• So D2: off & D3: On & C3: charged to 2Vmax through D3
• 4. For the next +ve half cycle
• D3: off & D4: On
• so C4: charged to 2Vmax through D4
• Then point D has 4 Vmax with respect to ground
• 5. For “2n” of capacitors
• The output voltage will be [2n Vmax]
• n: No. of stages
 Ripple Voltage
• For 3 stages
Voltage drop
Optimum number of stages