L7 DLD 27112023 111807am

DIGITAL LOGIC DESIGN (CEN-120) (3+1)
Faculty:
Shaista Ashraf
Computer Sciences Department,
Bahria University (Karachi Campus)
Summary
Latches
A latch is a temporary storage device that has two stable
states (bistable). It is a basic form of memory.
The S-R (Set-Reset) latch is the most basic type. It can be constructed
from NOR gates or NAND gates. With NOR gates, the latch responds
to active-HIGH inputs; with NAND gates, it responds to active-LOW
inputs.
R S
Q Q
Q Q
S R
NOR Active-HIGH Latch NAND Active-LOW Latch
Floyd, Digital
Floyd, Digital Fundamentals,
Fundamentals,1010 eded
th th
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Latches
The active-HIGH S-R latch is in a stable (latched) condition
when both inputs are LOW.
0 R 1
0
Assume the latch is initially RESET Q
(Q = 0) and the inputs are at their Latch
inactive level (0). To SET the latch initially
(Q = 1), a momentary HIGH signal RESET
0
1
is applied to the S input while the R Q
0 S
remains LOW.
0 R 1
0
To RESET the latch (Q = 0), a Q
momentary HIGH signal is Latch
applied to the R input while the S initially
remains LOW. SET
1
0
Q
0 S
Floyd, Digital
th th
Summary
Latches
The active-LOW S-R latch is in a stable (latched) condition
when both inputs are HIGH.
Assume the latch is initially RESET 1 S 1
0
Q
(Q = 0) and the inputs are at their
Latch
inactive level (1). To SET the latch initially
(Q = 1), a momentary LOW signal RESET
is applied to the S input while the R 1
0
1 R Q
remains HIGH.
To RESET the latch a momentary 1 S 1
0
Q
LOW is applied to the R input
Latch
while S is HIGH. initially
Never apply an active set and 1 SET
0
Q
reset at the same time (invalid). 1R
Floyd, Digital
th th
Summary
Latches
The active-LOW S-R latch is available as the 74LS279A IC.
It features four internal latches with (2)
1S1
two having two S inputs. To SET any (3) (4) 1Q
1S2
of the latches, the S line is pulsed low. (1)
1R
It is available in several packages. (6)
2S (7)
S-R latches are frequently used for 2Q
(5)
2R
switch debounce circuits as shown:
VCC (11)
3S1
(12) (9) 3Q
3S2
(10)
3R
(15)
2 S Q 4S (13)
S (14)
4Q
4R
R R Position Position
1 1 to 2 2 to 1
74LS279A
Floyd, Digital
th th
Summary
Latches
A gated latch is a variation on the basic latch.
The gated latch has an additional S
Q
input, called enable (EN) that must
be HIGH in order for the latch to
EN
respond to the S and R inputs.
Show the Q output with Q
relation to the input signals. R
Assume Q starts LOW.
Keep in mind that S and R are only active when EN is HIGH.
S
R
EN
Q
Floyd, Digital
th th
Summary
Latches
The D latch is an variation of the S-R latch but combines
the S and R inputs into a single D input as shown:
D D Q
Q
EN EN
Q
Q
A simple rule for the D latch is:

Q follows D when the Enable is active.
Floyd, Digital
th th
Summary
Latches
The truth table for the D latch summarizes its operation. If
EN is LOW, then there is no change in the output and it is
latched.
Inputs Outputs
D EN Q Q Comments
0 1 0 1 RESET
1 1 1 0 SET
X 0 Q0 Q0 No change
Floyd, Digital
th th
Summary
Latches D Q
EN
Determine the Q output for the
Q
D latch, given the inputs shown.
EN
Notice that the Enable is not active during these times, so

the output is latched.
Floyd, Digital
th th
Summary
Flip-flops
A flip-flop differs from a latch in the manner it changes
states. A flip-flop is a clocked device, in which only the
clock edge determines when a new bit is entered.
The active edge can be positive or negative.
D Q D Q
C C
Dynamic Q Q
input
indicator (a) Positive edge-triggered (b) Negative edge-triggered
Floyd, Digital
th th
Summary
Flip-flops
The truth table for a positive-edge triggered D flip-flop
shows an up arrow to remind you that it is sensitive to its
D input only on the rising edge of the clock; otherwise it is
latched. The truth table for a negative-edge triggered D
flip-flop is identical except for the direction of the arrow.
Inputs Outputs Inputs Outputs

D CLK Q Q Comments D CLK Q Q Comments
1 1 0 SET 1 1 0 SET
0 0 1 RESET 0 0 1 RESET
(a) Positive-edge triggered (b) Negative-edge triggered
Floyd, Digital
th th
Summary
Flip-flops
The J-K flip-flop is more versatile than the D flip flop. In
addition to the clock input, it has two inputs, labeled J and
K. When both J and K = 1, the output changes states
(toggles) on the active clock edge (in this case, the rising
edge).
Inputs Outputs
J K CLK Q Q Comments
0 0 Q0 Q0 No change
0 1 0 1 RESET
1 0 1 0 SET
1 1 Q0 Q0 Toggle
Floyd, Digital
th th
Summary
Flip-flops Q
J
CLK
Determine the Q output for the J-K
flip-flop, given the inputs shown. K Q
Notice that the outputs change on the leading edge of the clock.
Set Toggle Set Latch
CLK
Floyd, Digital
th th
Summary
Flip-flops
A D-flip-flop does not have a toggle mode like the J-K flip-
flop, but you can hardwire a toggle mode by connecting Q
back to D as shown. This is useful in some counters as you
will see in Chapter 8.
D Q
For example, if Q is LOW, Q is CLK CLK

HIGH and the flip-flop will toggle
on the next clock edge. Because the Q
flip-flop only changes on the active
edge, the output will only change
once for each clock pulse.
D flip-flop hardwired for
a toggle mode
Floyd, Digital
th th
Summary
Flip-flops
Synchronous inputs are transferred in the triggering edge
of the clock (for example the D or J-K inputs). Most flip-
flops have other inputs that are asynchronous, meaning
they affect the output independent of the clock.
PRE
Two such inputs are normally labeled
preset (PRE) and clear (CLR). These Q
J
inputs are usually active LOW. A J-K
flip flop with active LOW preset and CLK
CLR is shown.
K Q
CLR
Floyd, Digital
th th
Summary PRE
Flip-flops J Q
CLK
Determine the Q output for the J-K K Q

flip-flop, given the inputs shown.
CLR
Set Toggle Set Reset Toggle Latch
CLK
K Set
PRE Reset
CLR
Floyd, Digital
th th
Summary
Flip-flop Characteristics
Propagation delay time is specified for the rising and
falling outputs. It is measured between the 50% level of the
clock to the 50% level of the output transition.
50% point on triggering edge
CLK CLK 50% point
Q 50% point on LOW-to- Q 50% point on HIGH-to-

HIGH transition of Q LOW transition of Q
tPLH tPHL
The typical propagation delay time for the 74AHC family (CMOS)
is 4 ns. Even faster logic is available for specialized applications.
Floyd, Digital
th th
Summary
Another propagation delay time specification is the time
required for an asynchronous input to cause a change in the
output. Again it is measured from the 50% levels. The
74AHC family has specified delay times under 5 ns.
PRE 50% point CLR 50% point
Q 50% Q 50% point

point
tPHL tPLH
Floyd, Digital
th th
Summary
Set-up time and hold time are times required before and
after the clock transition that data must be present to be
reliably clocked into the flip-flop.
D
Setup time is the minimum
time for the data to be present CLK
before the clock.
Set-up time, ts
D
Hold time is the minimum
time for the data to remain after CLK
the clock.
Hold time, tH
Floyd, Digital
th th
Summary
Other specifications include maximum clock frequency,
minimum pulse widths for various inputs, and power
dissipation. The power dissipation is the product of the
supply voltage and the average current required.
A useful comparison between logic families is the speed-power
product which uses two of the specifications discussed: the average
propagation delay and the average power dissipation. The unit is energy.
What is the speed-power product for 74AHC74A? Use
the data from Table 7-5 to determine the answer.
From Table 7-5, the average propagation delay is 4.6 ns.
The quiescent power dissipated is 1.1 mW. Therefore, the
speed-power product is 5 pJ
Floyd, Digital
th th
Summary
Output
Flip-flop Applications lines
Q0
Principal flip-flop applications are for
D
temporary data storage, as frequency R
dividers, and in counters (which are D Q1

covered in detail in Chapter 8). C
Q2
Typically, for data storage applications, D
a group of flip-flops are connected to Parallel data

C
parallel data lines and clocked together. input lines R
Data is stored until the next clock pulse. D Q3

Clock C
R
Clear
Floyd, Digital
th th
Summary
Flip-flop Applications
For frequency division, it is simple to use a flip-flop in

the toggle mode or to chain a series of toggle flip flops to
continue to divide by two. HIGH HIGH
One flip-flop will divide fin

J QA J QB fout
by 2, two flip-flops will
divide fin by 4 (and so on). fin CLK CLK
A side benefit of frequency
division is that the output K K
has an exact 50% duty fin
cycle.
Waveforms:
fout
Floyd, Digital
th th
Selected Key Terms
Latch A bistable digital circuit used for storing a bit.

Bistable Having two stable states. Latches and flip-flops are
bistable multivibrators.
Clock A triggering input of a flip-flop.
D flip-flop A type of bistable multivibrator in which the output

assumes the state of the D input on the triggering
edge of a clock pulse.
J-K flip-flop A type of flip-flop that can operate in the SET,

RESET, no-change, and toggle modes.
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Selected Key Terms
Propagation The interval of time required after an input signal

delay time has been applied for the resulting output signal to
change.
Set-up time The time interval required for the input levels to be
on a digital circuit.
Hold time The time interval required for the input levels to
remain steady to a flip-flop after the triggering
edge in order to reliably activate the device.
Timer A circuit that can be used as a one-shot or as an
oscillator.
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

L7 DLD 27112023 111807am

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

L7 DLD 27112023 111807am

Uploaded by

Copyright:

Available Formats

DIGITAL LOGIC DESIGN (CEN-120) (3+1)

NOR Active-HIGH Latch NAND Active-LOW Latch

A simple rule for the D latch is:

Notice that the Enable is not active during these times, so

Inputs Outputs Inputs Outputs

(a) Positive-edge triggered (b) Negative-edge triggered

Set Toggle Set Latch

For example, if Q is LOW, Q is CLK CLK

Determine the Q output for the J-K K Q

CLK CLK 50% point

Q 50% point on LOW-to- Q 50% point on HIGH-to-

PRE 50% point CLR 50% point

Q 50% Q 50% point

temporary data storage, as frequency R

dividers, and in counters (which are D Q1

a group of flip-flops are connected to Parallel data

parallel data lines and clocked together. input lines R

Data is stored until the next clock pulse. D Q3

For frequency division, it is simple to use a flip-flop in

One flip-flop will divide fin

Latch A bistable digital circuit used for storing a bit.

D flip-flop A type of bistable multivibrator in which the output

J-K flip-flop A type of flip-flop that can operate in the SET,

Propagation The interval of time required after an input signal

You might also like