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DELD
DELD
RULES
1.
2.
3.
EXAMPLE
STEP - 1
STEP - 2
STEP - 3
STEP - 4
STEP - 5
STEP - 6
STEP - 7
ANS - 10000100
DEMORGAN'S
THEOREM 1-
THEOREM
It states that the complement of a product of variables is equal to
the sum of the complements of the vaiables .
• Logic diagram-
NOR Bubbled AND
!(A+B) !A.!B
THEOREM 2- It states that the complement of sum of variables is
equal to the product of the complements of the variables.
• Truth Table-
!(A+B)=!A.!B
A B !A !B A+B !(A+B) !A.!B
0 0 1 1 0 1 1
0 1 1 0 1 0 0
1 0 0 1 1 0 0
1 1 0 0 1 0 0
• Logic Diagram-
NAND Bubbled OR
!A+!B !(A.B)
UNIVERSAL LOGIC GATE
• Universal logic gates are the ones which can be used for implementing any gate like
AND ,OR and NOT , or any other combination of these basic gates . NAND and NOR gates
are known as universal gates, since any logic function can be implemented using NAND
or NOT gate.
1.NAND gate :- A logic circuit whose o/p is low when all inputs are high.
INPUT OUTPUT
A B Y=!(A.B)
0 0 1
0 1 1
1 0 1
1 1 0
2.NOR gate :- A logic circuit whose o/p is low when any one i/ps are high.
• TRUTH TABLE-
Logic diagram
A B Y=!(A+B)
0 0 1
0 1 0
1 0 0
1 1 0
Y=!(A.B)=!(X.X)=!X+!X=!X
Y=!(!A.!B)=A+B
• Truth Table:- • Logic Diagram-
A B !A.!B Y=!(!A.!B)
0 0 1 0
0 1 0 1
1 0 0 1
1 1 0 1
• Logic diagram
Y=!(A+B)=!(X+X)=!X
2.2 AND gate - 2.3 OR gate:-
Logic diagram
Logic diagram
Y=!(!A+!B)=A.B
Y=!(!(A+B))=A+B
0 0 1 0 0 0 1 0
0 1 1 0 0 1 0 1
1 0 1 0 1 0 0 1
1 1 0 1 1 1 0 1
QUINE-McCLUSKEY
MINIMIZATION TECHNIQUE
•Modern digital systems are designed using complex programmable logic devices , field
programmable gate arrays and large scale integrated circuits that can be configured by the end
users.This devices are highly complex and therefore the techniques required for designing digital
systems using these devices have to be computer driven rather than manual. A logic minimization
technique which has the following characteristics is therefore , required:
•The Quine-McCluskey minimization techniques satisfies the above requirements and hence
can be effectively used to design logic circuits . The K-map technique is not suitable for
handling the design of complex digital systems because of following disadvantages:
This is basically a tabular method of minimization and as much it is suitable for computer
applications. The procedure for optimization as follows:
Step 1: Describe individual minterms of the given expression by their equivalent binary
numbers.
Step 2: Form a table by grouping numbers with equivalent number of 1’s in them, i.e. first
numbers with no 1’s, then numbers with one 1, and then numbers with two 1’s, … etc.
Step 3: Compare each number in the top group with each minterm in the next lower group. If
the two numbers are the same in every position but one, place a check sign to the right of both
numbers to show that they have been paired and covered. Then enter the newly formed
number in the next column (a new table). The new number is the old numbers but where the
literal differ, an “_” is placed in the position of that literal.
Step 4: Using (3) above, form a second table and repeat the process again until no further
pairing is possible. (On second repeat, compare numbers to numbers in the next group that have
the same “_” position.
Step 5: Terms which were not covered are the prime implicants and are OR ed and AND ed
together to form final function.
Note: The procedure above gives you the prime implicant but not essential prime
Prime Implicants
• A product term that cannot have any of its
variables removed and still imply the logic
function is called a prime implicant.
1-10 10,14 X X
7,15 X X
-111
X X
111- 14,15
00— 0,1,2,3 X X X X
0,2,8,10 X X X X
-0-0
X X X X
0--1 1,3,5,7
F = !WZ+WXY+!X!Z
Prime Implicants
F = !WZ+WXY +!X!Z
YZ
WX 00 01 11 10
00 1 1 1 1
0--1
01 1 1
!WZ
11 1 1
111-
10 1 1
!X!Z
WXY
-0-0