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  • Floating Gate Mos Learning Array: GUIDE: Prof. DR. B.K Das

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    Suraj Choubey
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    This document summarizes a project on developing a floating gate MOS learning array. The project involved literature review on MOS learning arrays, layout construction of the floating gate MOS synapse and normalization circuit, software modeling of the floating gate MOS in subthreshold region, and brainstorming ideas. Key aspects of the floating gate MOS used include storing weight through electron tunneling or CHEI mechanisms. The document outlines the stages of the project, salient features of the floating gate MOS, block diagram of the learning array, normalization circuit layout, and concludes with references.

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    FLoating 8th Sem1

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    This document summarizes a project on developing a floating gate MOS learning array. The project involved literature review on MOS learning arrays, layout construction of the floating gate MOS synapse and normalization circuit, software modeling of the floating gate MOS in subthreshold region, and brainstorming ideas. Key aspects of the floating gate MOS used include storing weight through electron tunneling or CHEI mechanisms. The document outlines the stages of the project, salient features of the floating gate MOS, block diagram of the learning array, normalization circuit layout, and concludes with references.

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    22 views27 pages

    Floating Gate Mos Learning Array: GUIDE: Prof. DR. B.K Das

    Uploaded by

    Suraj Choubey
    This document summarizes a project on developing a floating gate MOS learning array. The project involved literature review on MOS learning arrays, layout construction of the floating gate MOS synapse and normalization circuit, software modeling of the floating gate MOS in subthreshold region, and brainstorming ideas. Key aspects of the floating gate MOS used include storing weight through electron tunneling or CHEI mechanisms. The document outlines the stages of the project, salient features of the floating gate MOS, block diagram of the learning array, normalization circuit layout, and concludes with references.

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    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
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    of 27

    FLOATING GATE MOS LEARNING ARRAY

    GUIDE : Prof. DR. B.K Das Presented by: Sushil Kumar Jain Priyadarshan Patra Rakesh Ranjan Dash Bhabani Shankar Hansdah Avinash Sahoo

    PROJECT :STAGES
    Literature study : MOS learning array
    Normalization circuit

    Layout construction: Floating gate MOS (synapse)


    Normalization Circuit Integration with Learning Array

    Software Modelling: Modelling Floating gate MOS in sub


    threshold region

    A neural synapse

    LEARNING IN NEURAL NETWORK

    SAILENT FEATURES OF FLOATING GATE MOS USED IN THIS PROJECT


    The Synapse stores a weight :

    SAILENT FEATURES
    Electron tunneling increase the weight since it removes electrons from the floating gate

    Itun = Ito e-( Vf / Vox )


    CHEI decreases the weight as it add electrons to the floating gate

    Ichei = Ise (Vdc / V inj )

    BLOCK DIAGRAM OF LEARNING ARRAY

    When the tunneling is occurring?


    X L L H H Y L H L H Output No tunneling TUNNELING No tunneling No tunneling

    Vox = Vtun - Vfg

    NORMALIZATION CIRCUIT

    Vd

    BRAIN STORMING : IDEAS

    EQUIVALENT CIRCUIT SUBTHRESHOLD REGION CAN BE MODELED LINEARLY UNDER PARTICULAR CONDITION

    Ig(tun) = Ito e-( Vf / Vox )


    Vox=Vtun-Vfg Ig (chei)= Ise (Vdc / V inj ) Vdc=Vds- o-Ut ln(Is/Io) Is = Io e(kQfg/CtUt) e(kVin/Ut)

    Ct=Cfs+Cfb+Cfd+Cfcg
    Qt=CtUt/k W=exp(Qfg/Qt)

    Is = Io e(kQfg/CtUt) e(kVin/Ut)
    Vdc=Vds- o-Ut ln(Is/Io) Ig (chei)= Ise (Vdc / V inj ) Vfg=(Qfg+(Cfd*Vd)+(Cfcg*Vcg))/Ctotal Ig(tun) = Ito e-( Vf / Vox ) Vox=Vtun-Vfg
    Ig(tun) = Ito e-( Vf / Vox ) Qfg=(Ichei-Itun)*t t=10ns Qfg=Qfg+Qfg

    SOFTWARE MODELLING

    Standards for the Tanner Tool


    Well minimum width well to well spacing minimum active width source/drain active to well edge well contact (active) to well edge poly minimum width poly to poly spacing gate extension out of active source drain width poly to active spacing active to p select/ n select select minimum width select to select spacing poly/active contact exact size Metal1 minimum width Metal overlap of poly/active contact : : : : : : : : : : : : : : : : 10 6 3 5 3 2 2 2 3 1 2 2 2 2 3 1

    Layout of a Floating Gate MOS

    The Normalization Circuit layout

    An array of MOS learning System

    Conclusion
    The layout of an 8X8 synapse array was drawn including the normalization circuit. A software model was developed using C to mimic the system The layout could not be simulated due to technical limitations. We are committed to take up the project forward and work on it till we reach the desired output.

    we learned and worked on tanner tool, C programming, circuit


    maker tools ,electronic bench during the course of this project.

    References :
    IEEE Trans A Floating-Gate MOS Learning Array with Locally Computed Weight Updates, Vol.44, No-12, Dec 1997 Chris Diorio, Student Member, IEEE, Paul Hasler, Student Member, IEEE Bradley A. Minch, Student Member, IEEE, and Carver A. Mead, Fellow, IEEE United States Patent by Diorio et al on Floating gate semiconductor structure. Patent No.: US 6,965,142 B2. Dated: 15th Nov, 2005. IEEE Trans on Adaptive CMOS: From Biological Inspiration to Systems-on-a-Chip CHRIS DIORIO, MEMBER, IEEE, DAVID HSU AND MIGUEL FIGUEROA Neaman A. Donald, Semiconductor physics and devices, 3rd edition, TMH. Kang Sung-Mo and Leblebici Yusuf, CMOS Digital Integrated Circuits3rd edition TMH. Gottgfried, Byron Promming with C , 2nd edition.

    Thank U

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