Low Power VLSI Design

Unit I

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MIS Structure

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Negative Bias
Accumulation

-qV

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Weak Inversion
Depletion

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Strong Inversion

• Strong Inversion
• Electron density at the surface > hole density NA in the bulk
• V (Strong inversion) VT
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Surface Space Charge Region

Charge Sheet Model

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Surface Space Charge Region

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Surface Space Charge Region

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Surface Space Charge Region

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Surface Space Charge Region

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εs = 11.7X8.85X10-14, εo = 3.9X8.85X10-14, Dn = 25 cm2 /s,

NA=1015/cm3, d=6nm, q=1.6X10-19, VDD = 2.5V, Z/L = 2/1,

Find VT = 0.63V

For applied voltage of 0.4V; φs = 0.4V, Find W

W = 71.95nm ; Wm = 88.12nm

IDst = 1.89nA, Qs =112.88µC, Qd = 11.5µC,

Qi = 101.39µC, ti = 2.385nm 11
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MIS – VG y

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Depth of Depletion Region

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Charge in the Inversion layer

Inversion of semiconductor surface starts from

In the operating temperatures of interest

Qs Charge/unit area in semiconductor

= Qi Charge/unit area in inversion layer +
Qd Charge/unit area in the depletion layer

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Inversion Layer Thickness – ti

Charge density in the inversion layer >> ionic charge density of bulk
Inversion layer is very thin

Majority of charge is contained within the distance over

which Φ drops by kT/q
At ti : Φ < kT/q of Φs ;
electron density < 1/e (0.37) of x=0

Φ across inversion layer is ~ kT/q (β)

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Inversion Layer Thickness – ti

Weak inversion : ; <<

Body Effect
VGS = VGB - VBS

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Subthreshold Current – nMOS

z
in the bulk

Relatively large
y
x

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Subthreshold Current – nMOS

Potential gradient along y axis, at source end y=0 : VSB = 0

at drain end y = L ; VDS -considered

at higher temp

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Subthreshold Current – nMOS

εs = 11.7X8.85X10-14, εo = 3.9X8.85X10-14, Dn = 25 cm2 /s,
NA=1015/cm3, d=6nm, q=1.6X10-19, VDD = 2.5V, Z/L = 2/1

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Subthreshold Swing
Gate depletion layer capacitance Insulator thickness

Depletion layer thickness

Sst ≈ 60mV at room temperature for d = 0

Sst ≈ 100mV at room temperature for sub micrometer MOS
iDst - 1µA/µm at VGS= VT = 0.6V to 1pA/1µm at VGS = 0

Sst – can be reduced by decreasing d or

substrate doping concentration
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Submicron MOS
Vt Independent of L, Z and VDS ; decreases with
L, increasing values of VDS,
IDst – Increases rapidly with VDS
VT Short Channel Length Effects
• VT decreases with reduced length L and increased VDS
• Doping concentration is increased to compensate reduction in
VT
• It leads to change in carrier mobility, IDST and device
characteristics
• Source and Drain depletion regions reduce - charge - Gate bias
for inversion
• Small VGS is required to turn on the device
• Drain depletion region expands into to substrate and VGS is
Lowreduced
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DIBL - Drain Induced Barrier Lowering

• Ex and Ey – Electric field vectors from gate and drain
• Ex- Vertical, Ey - Horizontal
• Ex is maximum at source end and decreases towards drain
• Ex(x,y) = Ex(0,y) at surface and 0 at bottom depletion region

• Condition of continuity of electric displacement vector

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DIBL - Drain Induced Barrier Lowering

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DIBL - Drain Induced Barrier Lowering

Short Channel Threshold Voltage Shift

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Narrow Gate Width Effects

Two effects increase VT ; one effect reduces VT

First effect

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Narrow Gate Width Effects

Second effect
•It is due to higher channel doping along width Z (channel stop
implant)
•This higher doping leads to higher VGS to invert the channel

Third effect
•Trench or fully recessed isolation
•Gate inversion layer is formed at the edges at lower voltages
than the centre, so VT is reduced

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Reverse Short Channel Effects

• Reduction in VT with L is not linear
• If L is reduced from 3µm VT increases till L ≈ 0.7µm
then VT decreases at a faster rate

Subsurface DIBL (Punch through)

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Gate Induced Drain Leakage

• VDG = VDD  Charge induced in drain depletion layer
• Substrate is at lower potential - the minority carriers are swept
laterally to substrate
• Non-equilibrium surface region – incipient inversion layer
• Non-equilibrium depletion layer – deep depletion layer
• If Eox is high, voltage drop across depletion layer leads to
tunneling in the drain via near-surface trap
• Several trap assisted tunneling are possible
• Minority carrier emitted into incipient inversion layer is laterally
moved to substrate
• completes the path for GIDL
• Contributes to standby power
• Controlled by oxide thickness or increasing doping in the drain
or eliminate traps
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εs = 11.7X8.85X10-14, εo = 3.9X8.85X10-14, Dn = 25 cm2 /s,

NA=1015/cm3, q=1.6X10-19, VDD = 2.5V,

Design MIS structure to get VT = 0.5V, Wm = 0.6µm,

IDst=5nA, φs = 0.2V, VFB=0.05V, ni = 1.08×1010 cm−3

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