Full swing complementary MOS/Bipolar Logic Circuit

• The BiCMOS ckt diagram

of a basic FS-CMBL 2-i/p
NAND gate is shown in
the figure.
• It consists of
complementary emitter-
follower configuration as a
driver for efficient driving.

• This ckt also consists of base-emitter shunting network

composed of MN3 and MP3 to achieve full o/p voltage
swing.
• MN4 and MP4 which are
inserted between X and Y
nodes acts as a
transmission gate.
• The combination of MN4
and MP4 is called CMOS
diode.

• When the both the i/p’s are high i.e. A=1, B=1 MN2, MN1
acts as a closed switches and discharge the node ‘Y’ to
GND.
• Non availability of MN3, Vout=VBE, on the availability of
MN3 Vout is further pull down to low value resulting QP1
turn off.
• Transmission gate will
ensure that QP1 will
remain in turn-off.
• When A is low i.e. A=0
MP2 turns ON and it
charges node X to VDD.

• Whenever the node X is at V DD, forces QN1 to enter

in to active region and the Vout=VDD-VBEon under the
absence of MP3.
• With MP3 Vout=VDD.
• Concurrently, a small part
of the drain current of
MP2 flows through MN4
to charge up the
capacitance of the node Y.

• As MN2 is off, this current will flow in to the base

of QP1 and depletes its base charge.
• In addition MN3 is ON to turn off QP1.
Drawbacks:
• During pull up phase a small portion of the base
current flows out to the o/p through MP3 without
any current amplification from QN1.

• During pull down phase the base current of QP1 is

reduced due to small current flow from the o/p
through MN3 in to the base of QP1.

• This occurrence degrades the ckt performance and

results in slower switching speed.
Full swing complementary MOS/Bipolar Logic Circuit
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