UNIT IV

Low-Voltage, Low-Power Logic Circuits-I:

i. Conventional CMOS logic gates
 Power dissipation in CMOS inverter
ii. Basic NAND and NOR gates
iii. Conventional BiCMOS logic gates
 BiCMOS Inverter
iv. Basic driver configurations.
v. Full swing with shunting devices
 Low-voltage, Low-power logic circuits
• This unit addresses the profound(penetrating or
entering deeply into subjects of thought or
knowledge) analysis on the development of the
CMOS and BiCMOS digital circuits for a low-voltage,
low-power environment.
• At the beginning some brief discussion on the
conventional CMOS and BiCMOS logic gates are
presented.
 CONVENTIONAL CMOS LOGIC GATES
CMOS technology provides superior performance in:
• Much smaller power dissipation, no static power
dissipation.
• Noise margins.
• Packing density.
• Ability to integrate large complex functions with high
yields.
• Significant decrease in the number of parts and
interconnections.
• Better speed and power performance.
• Lower cost of computing.
 POWER DISSIPATION IN CMOS TECHNOLOGY
The power dissipation in CMOS gate is:
• P = Psc+Ps+Pd
• Psc – short circuit power dissipation due to the
momentary existence of a direct path from power
supply to ground and the output of node switches.
• Ps – static power dissipation is the power consumed
during the intervals when the logic states remain
constant.
• Ideally this class of power dissipation does not
occur in the CMOS logic gate.
• Yet, in reality, because the MOS transistor is not a
perfect switch and there will always be leakage and
sub threshold current.
• Due to this a minimal contribution of the static
component to the total amount of dissipation.
• Pd – dynamic power dissipation is due to the
transient behavior of the CMOS gate while charging
and discharging the parasitic capacitive nodes of the
device.
• This accounts for atleast 90% of the total power
dissipation in CMOS gate.
 CONVENTIONAL BiCMOS LOGIC GATE
• permits performance optimization
• Higher degree of system integration
• Improved speed over CMOS
• Lower power dissipation than the bipolar
technology
• Drawbacks:
• Higher cost due to the added process complexity
• Greater process complexity incurs longer fabrication
cycle time as compared to either bipolar or CMOS
technology.
Basic Driver Configurations in the BiCMOS
Logic Circuit Family
Common Emitter BiCMOS driver configuration

Dis-Advantages:
• There will be an
additional delay caused
by saturated Q1 during
pull cycle, Q2 during pull
up cycle.
• Substantial stati power
dissipation during non
switching.
 Gated Diode driver configuration
Dis-Advantages:
• Restriction of the o/p
voltage swing from
(VDD-VBE) to VBE will
become crucial when
power supply voltage
scale down and leads to
degraded speed
performance.
• Lack of symmetry between tr anfd tf because
during pull down phase both NMOS, npn are fast;
during pull up phase both PMOS, pnp are slow.
 Emitter-Follower driver configuration

Advantages:
• Balanced tr and tf
because pull down ckt
consists of NMOS, pnp,
pull up ckt consists of
PMOS, npn are slow.
• Insensitive to Body-
effect.
Full swing with shunting devices
Full swing complementary MOS/Bipolar Logic Circuit
• The BiCMOS ckt diagram
of a basic FS-CMBL 2-i/p
NAND gate is shown in
the figure.
• It consists of
complementary emitter-
follower configuration as a
driver for efficient driving.

• This ckt also consists of base-emitter shunting network

composed of MN3 and MP3 to achieve full o/p voltage
swing.
• MN4 and MP4 which are
inserted between X and Y
nodes acts as a
transmission gate.
• The combination of MN4
and MP4 is called CMOS
diode.
• When the both the i/p’s are high i.e. A=1, B=1 MN2, MN1
acts as a closed switches and discharge the node ‘Y’ to
GND.
• Non availability of MN3, Vout=VBE, on the availability of
MN3 Vout is further pull down to low value resulting QP1
turn off.
• Transmission gate will
ensure that QP1 will
remain in turn-off.
• When A is low i.e. A=0
MP2 turns ON and it
charges node X to VDD.

• Whenever the node X is at V DD, forces QN1 to enter

in to active region and the Vout=VDD-VBEon under the
absence of MP3.
• With MP3 Vout=VDD.
• Concurrently, a small part
of the drain current of
MP2 flows through MN4
to charge up the
capacitance of the node Y.

• As MN2 is off, this current will flow in to the base

of QP1 and depletes its base charge.
• In addition MN3 is ON to turn off QP1.
Drawbacks:
• During pull up phase a small portion of the base
current flows out to the o/p through MP3 without
any current amplification from QN1.

• During pull down phase the base current of QP1 is

reduced due to small current flow from the o/p
through MN3 in to the base of QP1.

• This occurrence degrades the ckt performance and

results in slower switching speed.
Full swing complementary MOS/Bipolar Logic Circuit
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