Chapter 7 -- Modular Sequential Logic

Serial-in, Serial-out Shift Register

C e ll n xn C e ll i xi C e ll i-1 x i-1 C e ll 1 x1

S e r ia l in S e r ia l o u t
M S M S M S M S

S h ift
c o n tr o l
p u lse
(a )

S e r ia l in S e r ia l o u t
S Q S Q S Q
CK CK CK
R Q R Q R Q

S h ift

(b )
 Generic Shift Register
P a r a llel in (Y )
P a r a llel o u t (X )

S e r ia l in n -B it sh ift S e r ia l o u t
r e g iste r

P r e se t c o n tr o l
S h ift p u lse
C le a r c o n tr o l
(a )

P a r a llel in (Y ) P a r a llel o u t (X )

S e r ia l o u t S e r ia l in n -B it sh ift
n -B it sh ift
r e g iste r r e g iste r

P r e se t c o n tr o l
S h ift p u lse S h ift p u lse

C le a r c o n tr o l C le a r c o n tr o l
(b ) (c )
SN74164 Serial-in, Serial-out Shift Register
(9 )
C le a r
(8 )
C lo c k
(1 )
S e r ia l A C le a r C le a r C le a r C le a r C le a r C le a r C le a r C le a r
R R R R R R R R
in p u ts B QA QB QC QD QE QF QG QH

(2 ) CK CK CK CK CK CK CK CK
S QA S QB S QC S QD S QE S QF S QG S QH

(3 ) (4 ) (5 ) (6 ) (1 0 ) (1 1 ) (1 2 ) (1 3 )
O u tp u t O u tp u t O u tp u t O u tp u t O u tp u t O u tp u t O u tp u t O u tp u t
QA QB QC QD QE QF QG QH
(a ) (S er ia l o u tp u t)

C le a r
S e r ia l A
in p u ts B
C lo c k
QA
QB
QC
O u tp u ts QD
QE
QF
QG
C le a r C le a r
(b )
SN74164 Function Table and Package

A 1 14 V CC

In p u ts O u tp u ts B 2 13 QH
C le a r C lo c k A B QA QB É QH
QA 3 12 QG
L ´ ´ ´ L L L
H L ´ ´ Q A0 Q B0 Q H0 QB 4 11 QF
H ­ H H H Q An Q Gn
H ­ L ´ L Q An Q Gn
H ­ ´ L L Q An Q Gn QC 5 10 QE

QD 6 9 C le a r
Q A 0 , Q B 0 , Q H 0 = le v e ls o f Q A , Q B , Q H , r e sp e c tiv e ly ,
b e fo r e th e in d ic a te d ste a d y -sta te in p u t c o n d itio n s a r e e sta b lish e d .
Q A n , Q G n = le v e ls o f Q A , Q G , r e sp e c tiv e ly , b e fo r e th e m o st GND 7 8 C lo c k
r e c e n t ­ tr a n sitio n o f th e c lo c k (1 -b it sh ift)
(c ) (d )
SN74165 8-bit Serial-In, Serial-out Shift register
P a r a lle l in p u ts

A B C D E F G H
(1 ) (1 1 ) (1 2 ) (1 3 ) (1 4 ) (3 ) (4 ) (5 ) (6 )
S h ift/L o a d

(1 5 )
C lo c k in h ib it
C lo c k
(2 )
S S S S S S S S (9 )
QH
CK CK CK CK CK CK CK CK
(1 0 ) (7 )
S e r ia l D D D D D D D D QH
R R R R R R R R

(a )

A
(1 ) (1 1 )
S h ift/L o a d

(1 5 )
C lo c k in h ib it
C lo c k
(2 )
S
CK
(1 0 )
S e r ia l D
R

(b )

In p u ts In te r n a l O u tp u t
S h ift/ C lo c k P a r a lle l o u tp u ts
lo a d in h ib it C lo c k S e r ia l A ...H QA QB QH
L ´ ´ ´ a ...h a b h
H L L ´ ´ Q A0 Q B0 Q H0
H L ­ H ´ H Q An Q Gn
H L ­ L ´ L QAn Q Gn
H H ´ ´ ´ Q A0 Q B0 Q H0

(c )
 SN74165 Timing Diagram
C lo ck

C lo ck in h ib it

S erial in p u t L

S h ift/lo ad

A H
L
B

C H

L
D
D ata
E H

F L

G H

H H

O u tp u t Q H H H L H L H L H

L L H L H L H L
O u tp u t Q H
S erial sh ift

L o ad
In h ib it
(d )
 Parallel Accumulator

xn x2 x1
...

FA FA HA

Q D Q D Q D

CK ... CK CK
CLR CLR CLR

... C lear
A ccu m u late

z n+ 1 z n z2 z1
(b )
 Synchronous Binary Counter
Xn X3 X2 X1

...

O v erflo w Q J Q J Q J Q J 1
CK CK CK CK
Q K Q K Q K Q K
CLR CLR CLR CLR

... C lear

Count
... In h ib it
(a)

Xn X3 X2 X1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0

1 1 1 0
1 1 1 1
R ecy cles
0 0 0 0
0 0 0 1
0 0 1 0

(b )
SN74163 Synchronous Binary Counter
(9 )
L o ad
(1 4 )
J Q QA

CK
(3 )
D a ta A K

(1 3 )
J Q QB

CK
(4 )
D a ta B K
(2 )
C lo ck

(1 2 )
J Q QC

CK
(5 )
D a ta C K

(1 1 )
J Q QD

CK
(6 )
D a ta D K
(1 )
C lear

(7 )
ENP
ENT (1 5 )
(1 0 ) RCO

(a)

In p u ts
C lear L o ad ENT ENP M ode
L ´ ´ ´ S y n ch ro n o u s clear
H L ´ ´ S y n ch ro n o u s lo ad
H H H H Count
H H L  H o ld
H H  L H o ld

(b )
 SN74163 Timing Diagram
C lear
L o ad

D ata B
in p u ts
C
D
C lo ck

ENP
ENT

QA
QB
O u tp u ts
QC
QD

RCO
12 13 14 15 0 1 2
Sync Count In h ib it
clear
Sync
lo ad
(c)
 Asynchronous Down Counter
Xn ... X3 X2 X1 Xn ... X3 X2 X1

1 ... 1 1 1 0 ... 0 0 0
0 ... 0 0 0 1 ... 1 1 1
0 ... 0 0 1 1 ... 1 1 0
0 ... 0 1 0 1 ... 1 0 1
0 ... 0 1 1 1 ... 1 0 0
0 ... 1 0 0 1 ... 0 1 1
U p count m ode D ow n count m ode

(a )

Xn X2 X1

... Count

Q J Q J Q J

CK ... CK CK

Q K Q K Q K
CLR CLR CLR C lo c k

... C le a r

(b )
 Synchronous Up/Down Counter
Xn X2 X1

... U p /d o w n
...

Q J Q J Q J 1
Up
o v erflo w CK CK CK
Q K Q K Q K
CLR CLR CLR

...
...
Down ... C lo ck
o v erflo w

... C lear
SN74160 Synchronous Decade Counter

'1 6 0
(1 ) C T R D IV 1 0
C lear 1 16 V CC C lear CT = 0
(9 )
L o ad M1
C lo ck 2 15 RCO
M2 (1 5 )
3 14 (1 0 ) 3CT = 9 RCO
A QA ENT G3
(7 )
B 4 13 QB ENP G4
(2 )
C lo ck G 5 /2 ,3 ,4 +
C 5 12 QC
(3 ) (1 4 )
D 6 11 QD A 1 ,5 D (1 ) QA
(4 ) (1 3 )
B (2 ) QB
ENP 7 10 ENT (5 ) (1 2 )
C (4 ) QC
GND 8 9 L o ad (6 ) (1 1 )
D (8 ) QD

(a) (b )
 SN74160 Logic Diagram
(9 )
L o ad
(1 4 )
J Q QA

CK
(3 )
D a ta A K CLR

(1 3 )
J Q QB

CK
(4 )
D a ta B K
CLR
(2 )
C lo ck

(1 2 )
J Q QC

CK
(5 )
D a ta C K
CLR

(1 1 )
J Q QD

CK
(6 )
D a ta D K Q
CLR
(1 )
C lear

(7 )
ENP
ENT (1 5 )
(1 0 )
RCO

(c)
 SN74160 Timing Diagram
C lear
L o ad

D ata B
in p u ts C
D
C lo ck

ENP
ENT

QA
QB
O u tp u ts
QC
QD

RCO
7 8 9 0 1 2 3
A sy n c
clear Count In h ib it
Sync
lo ad
(d )
Asynchronous BCD Counter
X3 X2 X1 X0

C ount

S S S S
Q J Q J Q J Q J
CK CK CK CK C lo c k
Q K Q K Q K Q K
R R R R

C le a r

(a )

0
1
0 2
10

8
3
9 2

8 4

0
5
7
4 6
6
4
(b )
 Digital Timer Block Diagram
M in u te s Seconds

1 P u lse /h o u r 1 P u lse /m in u te

¸6 ¸ 10 ¸6 ¸ 10

C le a r

S ta r t/S to p
¸5 ¸ 12

P u lse
g e n e r a to r 1 P u lse /se c o n d

P o w e r lin e

Figure 7.22
SN7492A Asynchronous Counter
(1 2 )
J Q QA
C lo c k B 1 14 C lo c k A
(1 4 )
C lo c k A CK
NC 2 13 NC
K
NC 3 12 QA

NC 4 11 QB
(1 1 )
J Q QB
V CC 5 10 GND
(1 )
C lo c k B CK
R O (1 ) 6 9 QC
K
R O (2 ) 7 8 QD

(a ) (9 )
J Q QC

'9 2 CK
(6 ) & CTR
R O (1 ) K Q
(7 ) CT = 0
R O (2 )
(8 )
(1 4 ) J Q QD
D IV 2 (1 2 )
C lo c k A + QA
CK
D IV 3 11
(1 ) 0 QB
C lo c k B + CT (9 ) K
1Z4 QC
(6 )
(8 ) R 0 (1 )
D IV 2
4+ QD R 0 (2 )
(7 )
(b ) (a )
 SN7492A Timing Diagram

C lo c k B

R 0 (1 ) = R 0 (2 )

QB 0 1 0 0

QC 0 0 1 0

JB = Q C 1 1 0 1

KB 1 1 1 1
JC = Q B 0 1 0 0
KC
1 1 1 1

(d )
SN7492A State Diagrams
0
8
1
12
0 2

13

3
2
12

10 4

11
5

10
4
9 8
0
8
(e )

8
12 1
0 2
0
14

13

12
6

8
10 4
9 8
0

(f)
Modulo-N Asynchronous Counter
X n- 1 X1 X0

C ount
c o n tr o l

S S S
Q J Q J Q J
CK CK CK C ount
p u lse
Q K Q K Q K
R R R

S ta te d etec tio n C le a r
lo g ic c o n tr o l
 SN74293 Asynchronous Binary Counter
(9 )
J QA QA
0
(1 0 )
In p u t A CK 8 0 1
2

K 12
3
14 2
(5 )
J QB QB
15 0
(1 1 )
In p u t B CK
4
K 14

5
(4 ) 12
J QC QC 13 4

CK
6
K 12

8
7
11
(8 ) 10
J QD QD 6

CK 4
10
0
K 9 8
(1 2 ) 8
R 0 (1 )
R 0 (2 )
(1 3 )
(a ) (b )
Modulo-13 Counter Design -- Example 7.1
74293
C lo c k In p u t A QA
In p u t B QB
QC
QD
R 0 (1 )
R 0 (2 )
7 4 1 1 /3

7 4 3 2 /4

C le a r
(a )

13 0
1
0 2

12
8
3
10 2
11
0
4

10

5
8
9
6
8 4
7

0 6
4
(b )