Complementary MOS fabrication

CMOS Technology depends on using both N-Type and P-Type devices on the same chip.
The two main technologies to do this task are:
 P-Well
The substrate is N-Type. The N-Channel device is built into a P-Type well within the
parent N-Type substrate, The P-channel device is built directly on the substrate.
 N-Well
The substrate is P-Type. The N-channel device is built directly on the substrate.
while the P channel device is built into a N-type well within the parent P-Type substrate.

Two more advanced technologies to do this task are:

Becoming more popular for sub-micron geometries where device performance and
density must be pushed beyond the limits of the conventional p & n-well CMOS
processes
 Twin Tub
Both an N-Well and a P-Well are manufactured on a lightly doped N-type substrate
 Silicon-on-Insulator (SOI) CMOS Process
SOI allows the creation of independent, completely isolated nMOS and pMOS
 Why to study Fabrication?
• Strong link between Fabrication Process , the circuit design
procedure and the performance of resulting chip

• The circuit designer must have clear understanding of the roles

of various MASKs used in the fabrication procedure and How
this MASKs define various feature of the devices on a Chip

• To know to create effective design.

• To optimize the circuit with respect to various manufacturing

parameters.
 Well
• Requires to build both pMOS and nMOS on single wafer.

• To accommodate both pMOS and nMOS devices, special

regions must be created in which the semiconductor type is
oppossite of the substrate type.

• Also Known as Tubs.

• Twin-tubs
Flow Diagram
Create n-Well regions and
Channel Stops region

Grow Field Oxide and

Gate Oxide

Deposite and pattern

Polysilcon Layer

Implant sources, drain regions

and substrate contacts

Create contact Windows,

deposit and pattern metal layer
 Fabrication Procedure Flow: Basic Steps
• Masks: Each Processing steps in the fabrication procedure requires to
define certain area on the chip. This is known as Masks.
• Chips are specified with set of masks
• Minimum dimensions of masks determine transistor size (and hence
speed, cost, and power)
• Feature size f = distance between source and drain
– Set by minimum width of polysilicon
• Feature size improves 30% every 3 years or so
• Normalize for feature size when describing design rules
• The ICs are viewed as a set of pattern layers of doped Silicon,
Polysilicon, Metal and Insulating Silicon Dioxide.
• A layer mut be Patterned before the next layer of material is applied on
the chip.
 Inverter Cross-section
• Typically use p-type substrate for nMOS transistors

• Requires n-well for body of pMOS transistors

A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

Inverter Cross-section with Well and Substrate taps

• Typically use p-type substrate for nMOS transistors

• Requires n-well for body of pMOS transistors
• Substrate must be tied to GND and n-well to VDD
• Metal to lightly-doped semiconductor forms poor connection
• Use heavily doped well and substrate contacts / taps
A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap

 Inverter Mask Set
• Transistors and wires are defined by masks
• Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap
 Detailed Mask Views
• Six masks n well

– n-well
– Polysilicon Polysilicon

– n+ diffusion n+ Diffusion

– p+ diffusion p+ Diffusion

– Contact Contact

– Metal
Metal
 Fabrication Steps
• Start with blank wafer
• Build inverter from the bottom up
• First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2

p substrate
 Oxidation
• Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate
Photolithography

Exposure Processes
 Photoresist
• Used for lithography .
• Lithography is a process used to transfer a pattern to layer on the chip.
Similar to Printng Process
• Spin on photoresist (about 1 mm thickness)
– Photoresist is a light-sensitive organic polymer
– Possitive Photoresist: Softens where exposed to light
– Negative Photresist: Harden where exposed to light, Not used in
practise generally

Photoresist
SiO2

p substrate
 Lithography
• Expose photoresist through n-well mask
• Strip off exposed photoresist

Photoresist
SiO2

p substrate
 Etch
Cluster Tool Etch
Configuration Chambers

Wafers Transfer
Chamber

Loadlock

RIE Chamber Gas Inlet

Die-electric Etch
Wafer
Transfer
Plasma Etch Chamber
RF Power

Exhaust
 Etch
• Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
• Only attacks oxide where resist has been
exposed

Photoresist
SiO2

p substrate
 Strip Photoresist
• Strip off remaining photoresist
– Use mixture of acids called piranah etch
• Necessary so resist doesn’t melt in next step

SiO2

p substrate
 n-well
• n-well is formed with diffusion or ion implantation
• Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
• Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
SiO2

n well
 Ion Implantation
Focus Beam trap and Neutral beam and
gate plate beam path gated

Neutral beam trap Y - axis X - axis Wafer in wafer

and beam gate scanner scanner process chamber

phosphorus
(-) ions photoresist mask

f ield oxide
n-w ell p- epi
p-channel transistor
p+ substrate
 Strip Oxide
• Strip off the remaining oxide using HF
• Back to bare wafer with n-well
• Subsequent steps involve similar series of steps

n well
p substrate
 Polysilicon
• Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
• Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate
 Polysilicon Patterning
• Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate
 Self-Aligned Process
• Use oxide and masking to expose where n+ dopants should be
diffused or implanted
• N-diffusion forms nMOS source, drain, and n-well contact

n well
p substrate
 N-diffusion
• Pattern oxide and form n+ regions
• Self-aligned process where gate blocks diffusion
• Polysilicon is better than metal for self-aligned gates because
it doesn’t melt during later processing

n+ Diffusion

n well
p substrate
 N-diffusion cont.
• Historically dopants were diffused
• Usually ion implantation today
• But regions are still called diffusion

n+ n+ n+
n well
p substrate
 N-diffusion cont.
• Strip off oxide to complete patterning step

n+ n+ n+
n well
p substrate
 P-Diffusion
• Similar set of steps form p+ diffusion regions for pMOS source
and drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+
n well
p substrate
 Contacts
• Now we need to wire together the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate
 Metalization
• Sputter on aluminum over whole wafer
• Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate
 Stick Diagrams

Stick Diagrams
• Objectives:
– To know what is meant by stick diagram.
– To understand the capabilities and limitations of stick
diagram.
– To learn how to draw stick diagrams for a given MOS
circuit.

• Outcome:
– At the end of this module the students will be able
draw the stick diagram for simple MOS circuits.
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 Stick Diagrams

Stick Diagrams

N+ N+

33
S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
 Stick Diagrams

Stick Diagrams
VDD
VDD
X

X
x x x
x Stick
Diagram X

Gnd Gnd

34
 Stick Diagrams

Stick Diagrams

VDD
VDD
X

X
x x x
x X

Gnd Gnd

35
 Stick Diagrams

Stick Diagrams
• VLSI design aims to translate circuit concepts
onto silicon.
• stick diagrams are a means of capturing
topography and layer information using simple
diagrams.
• Stick diagrams convey layer information
through colour codes (or monochrome
encoding).
• Acts as an interface between symbolic circuit
and the actual layout.
36
 Stick Diagrams

Stick Diagrams

 Does show all components/vias.

 It shows relative placement of components.
 Goes one step closer to the layout
 Helps plan the layout and routing

A stick diagram is a cartoon of a layout.

37
 Stick Diagrams

Stick Diagrams

 Does not show

• Exact placement of components
• Transistor sizes
• Wire lengths, wire widths, tub boundaries.
• Any other low level details such as parasitics..

38
 Stick Diagrams

Stick Diagrams – Notations

Metal 1

poly

ndiff

pdiff
Can also draw
in shades of
gray/line style.

Similarly for contacts, via, tub etc..

39
 Stick Diagrams

Stick Diagrams – Some rules

Rule 1.
When two or more ‘sticks’ of the same type
cross or touch each other that represents
electrical contact.

40
 Stick Diagrams

Stick Diagrams – Some rules

Rule 2.
When two or more ‘sticks’ of different type cross or
touch each other there is no electrical contact.
(If electrical contact is needed we have to show the connection explicitly).

41
 Stick Diagrams

Stick Diagrams – Some rules

Rule 3.
When a poly crosses diffusion it represents a
transistor.

Note: If a contact is shown then it is not a transistor.

42
 Stick Diagrams

Stick Diagrams – Some rules

Rule 4.
In CMOS a demarcation line is drawn to avoid
touching of p-diff with n-diff. All pMOS must
lie on one side of the line and all nMOS will
have to be on the other side.

43
 Stick Diagrams

How to draw Stick Diagrams

44
2 Input NAND GATE
2 Input NOR Gate
Boolean Expression
Stick Diagrams

Power

A Out

Ground

52
Layout Design Rules
SHEET RESISTANCECE Rs

1) Consider their interconnection as circuits.

2) of the resistive and capacitive characteristics of each layer.
3) Concepts such as sheet resistance Rs and a standard unit of capacitance DCg,
help greatly in evaluating the effects of wiring and _input and output capacitances.

Consider a uniform slab of conducting material of

• resistivity p, of width W, thickness t, and length between faces L.
SHEET RESISTANCE CONCEPTAPPLIED TO MOS TRANSISTORS AND INVERTERS
 AREA CAPACITANCES OF LAYERS

For any layer, knowing the dielectric (silicon dioxide) thickness, we can calculate area
capacitance as follows:
 STANDARD UNIT OF CAPACITANCE Cg
•It is convenient to employ a standard unit of capacitance that can be given a value

appropriate

to the technology

•But can also be used in calculations without associating it with an absolute value.

•The unit is denoted Cg and is defined the gate-to-channel capacitance of a

MOS transistor having W = L = feature size, that is, a 'standard' or 'feature size' square
Table: 4.2
SOME AREA CAPACITANCE CALCULATIONS