ECE3620Unit 8

ECE 3620
Introduction to Microcomputers
© 2016, Macam S Dattathreya, PhD

Wayne State University
Electrical and Computer Engineering
1
Course Topics
Unit Topic Duration
(weeks)
1 Microcomputer Execution of Assembly Programs: A Brief 1
Overview
2 Instructions, Addressing Modes, Data Representation, 2
Arithmetic and Logic, Branching, and Simple Assembly
Programs
3 68HC11 Assembly Programming and Development Tools 2
4 Stacks, Subroutines and Data Structures 2
5 The Hardware Configuration and Interrupts 1
6 Parallel I/O – Ports B and C 1

7 The Analog-to-Digital Converter – Port E 1
8 The Timing System and Port A 2
© 2016, Macam, Introduction to Microcomputers 2

Unit #8
The Timing System and Port A

Table of Contents
• Timing System
• The Free-Running Counter
• Real-Time Interrupts
• Port A: Simple Mode of Operation
• Input Capture Function
• Output Compare Function
• The Pulse Accumulator

68HC11: Timing Requirement
• Delay creation and measurement
• Period measurement
• Event counting
• Time-of-day tracking
• Periodic interrupt generation
– Remind processor to perform other tasks
• Waveform generation

Timing System of 68HC11
• Timers generate waveforms
– Varying frequencies
– Five output timers
• Counters count certain events on the input
lines
– E.g., rising edges of signal

• Controlled by a crystal oscillator
– E-Clock: ¼ of crystal frequency
• 8 MHz clock (EVBPlus2) & E clock : 2 MHz:
– Each instruction cycle time : 0.5 µs
• Timing controls rate of instruction execution
and most of Input/output
– Port A: Timer & counter hardware implementation

EXTAL
CPU Core
XTAL
Timer &
counter system
Port A
68HC11
Crystal Oscillator: Creates an electrical signal with

precise frequency

• Timers generate waveforms
– Varying frequencies
– Five output timers
• Independent configuration settings
• Programmable to take actions on output pins
– E.g., Do nothing, set output to high/low, or invert the output
values

Timer System of 68HC11
• 16-bit free running main timer (counter)
– Performs many functions
• Real time interrupt (RTI)
• Three input capture functions
• Five output-compare functions
• 8-bit pulse accumulator
• More discussions to follow


The Free Running Counter
Cleared at RESET; Control Registers &
After this is Read only E clock their memory locations
@ 2 MHz
Time resolution: 0.5µs
Timer Counter (TCNT) Register (16-Bit)

(TCNTH)
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 $100E
(TCNTL)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $100F
Incremented @ every tick of the E clock (cannot 216 = 65,536 counts to cycle it around
writtenAlways
Note: read TCNT as a 16-bit number using once
by the program) LDD,i.e.,
LDX, or LDY $100E
@ 2 MHz, 65536 * 0.5 µs = 32.768 ms
instruction; Reading 8-bit portions separately gives erroneous results. When
Higher bytes are read, the counter freezes the lower byte of the register. This
assures the results are always read in two bytes and are correct
Note: The returned count value on a double-byte read corresponds
to the value of the free running counter at the second-to-last cycle
of the double-byte read instruction.
• Example: Assume TCNT = $01FB before executing

the following program segments:
Segment#1:
LDD $100E
Segment#2
LDAA $100E
LDAB $100F
what will be in ACCA and ACCB after these instructions?
Before Program Segment#1
Timer Counter (TCNT) Register (2-Bytes)
TCNTH $01 $FB TCNTL
$100E $100F
Execute the instruction LDD $100E (Requires 5 cycles to read)

Cycle#3
Cycle#5
Cycle#4
Cycle#2
Cycle#1
TCNTH $01
$02 $FD
$FC
$FE
$FF
$00 TCNTL
$100E $100F
D Register
$01FF
Read High-byte into D
register, Low-byte is
Note: The TCNT is incremented by 1 after E cycle 5 i.e., after
frozen
LDD instruction
This means if you use
this, ACCA = $01 and Note: The TCNT still reflects the exact
ACCB = $FF number of E clock ticks; so, TCNT has $0200
after LDD
• Solution: First Segment
– Recall: The lower byte of the TCNT register is
frozen when higher byte is being read in a 16-bit
read of the TCNT register
– In extended mode, LDD requires 5 cycles
– Loads the high byte in the 4th cycle
– At the 4th cycle, TCNT = $01FF
• This value is frozen and read into D register
• So, ACCA gets $01 and ACCB gets $FF
• Note: The TCNT still reflects the exact number of E
clock ticks; so, TCNT has $0200 after LDD

Before Program Segment#2
Timer Counter (TCNT) Register (2-Bytes)
TCNTH $01 $FB TCNTL
$100E $100F
Execute the instruction LDAA $100E (Requires 4 cycles to read)

Cycle#3
Cycle#5
Cycle#7
Cycle#2
Cycle#1
Cycle#4
Cycle#8
Cycle#6
ACCA
$01 TCNTH $01
$02 $FD
$03
$00
$FC
$FE
$FF
$02
$01 TCNTL
$100E $100F
ACCB
$03 Read High-byte
Read Lowinto ACCA
-byte into&ACCB
next
tick happens, the next instruction
LDAB $100F happens
These results are TCNT register can keep track of time, also used to implement time delays,
not correct But, implementing time delays using TCNT might not be simple (example
next)
• Solution: Second Segment
– LDAA requires 4 cycles
• Reads $100E during the fourth cycle
• But TCNT increments with every cycle, so TCNT will be
$01FF when read and ACCA = $01
– Next, LDAB reads $100F, four cycles later when
TCNT = $0203, and ACCB gets $03
– The result of the read is $0103 Not close to the
correct result

• Example:
An increment of 10000 (decimal) in the TCNT
register corresponds to 0.5 µs * 10000 = 5 ms. This
subroutine utilizes the free-running timer in to
implement a 5 ms delay:

Reads TCNT register

values to D register
Adds 5 ms to D
register
Reads TCNT register

Continuously until it is
larger than register D
What is wrong with this program?

Problem#1: TCNT could go negative value by
adding 10000 delay, so BGT (signed comparison)
miss functions.
Resolution: Use BHI instruction (unsigned
comparison)
Problem#2: 16-bit addition limitation. Overflow may occur (for other

delays, the sum may be smaller than TCNT’s current value). E.g., TCNT =
$8000; TCNT + $9000 (delay) = $1000; Here BHI also miss functions
Resolution: Check the C bit in the CCR
Problem#3: Longest delay in this approach: 32.77 ms. HC11 will be

100% busy implementing this delay!
Resolution: User program must keep track of the number of timer
overflows to generate longer delays

Timer Overflow
• A program cannot reset the counter (TCNT)
• The TCNT increments with each E clock cycle
till it rolls over from $FFFF to $0000
– and keeps incrementing beyond $0000
– Every time the TCNT rolls over the TOF (Timer
Overflow) bit is set in TFLG2
– The Timer Flag (TFLG2) register is at $1025 and
TOF is its bit 7: TOF will be set every 32.77 ms

Timer Overflow

Timer Overflow
• TOF, are cleared by writing a 1 into the bit
position of the flag!
– TOF can then be cleared by simply storing $80 at
$1025 (TFLG2)
• Bit 7 of TMSK2, the register at location $1024,
is TOI (Timer Overflow Interrupt)
– This is the interrupt bit that is the companion to
TOF
– If TOI is set, the 68HC11 will interrupt whenever
TOF sets

Timer Overflow
• Timer overflow interrupt vector is at $FFDE and $FFDF (see
below)

Timer Overflow
• EVBplus2: Three bytes between $00D0 and $00D2 (jump-to-
the-service-routine instruction in response to a TOI)

Timer Overflow: Programming Example1
• Write a program that toggles the LED
connected to PB0 every about 500 ms. Employ
the TOI
• Solution:
– The 68HC11 timer overflows every 32.77 ms and
causes the TOF bit in TFLG2 to set to 1
– If TOI is set to 1, a TOI interrupt is sent to the
68HC11

• Solution:
– This interrupt will be served if the I-bit in the CCR
is unmasked (i.e., I = 0)
– 500 ms is approximately 15 loops around at a
32.77 rate
– This routine toggles PB0 and clears TOF by writing
a one in it
– This prepares the 68HC11 for the next TOI
– Program is next

• This program generates a square wave

on PB0
• The period of this wave is 1 sec. Its
frequency is 1/1 sec = 1 Hz

68HC11: Real-Time Interrupts (RTI)
• The 68HC11 periodically generates real-time
interrupts (RTI; not to be confused with the RTI
instruction)
• Each real-time interrupt sets the RTIF flag (bit 6)
in TFLG2 (at $1025)
• The RTI rate of interrupt can be selected by the
user
– The four RTI rates depend on the setting of the RTR1
and RTR0 bits (bits 1 and 0, respectively) in the
Pulse Accumulator Control (PACTL) register at $1026
68HC11: Real-Time Interrupts

• Upon RESET, RTR1 and RTR0 default to 0
– i.e., RTI rate is 4.10 ms by default. If both RTR bits
are 1, the RTI rate is 32.77 ms, the same rate as
TOF

• A real-time interrupt does not actually
interrupt
– it just sets the RTIF flag in TFLG2 (bit 6)
– If , RTII (bit 6 in TMSK2), is set, the RTII will
interrupt
– EVBPlus2: The interrupt vector @ $FFF0 and $FFF1
and the pseudo-vector @ $00EB-00ED
– When real-time interrupts are used, the RTIF flag
must be cleared by the ISR before the RTI (Return
from Interrupt) instruction is executed

Real-Time Interrupts: Programming Example2
• Repeat Example 1 employing real-time interrupts.
Assume an RTI rate of 8.19 ms
• Solution:
– The 68HC11’s real time interrupt rate of 8.19 ms requires
to set RTR1 to 0 and RTR0 to 1
– To delay for 500 ms requires approximately 61 loops
around at a 8.19 ms rate
– Here, we need to deal with three registers:
• (1) Set RTR1 and RTR0 to 0 and 1, respectively
– This is achieved by storing $01 in PACTL at $1026
• (2) Clear the real-time interrupt flag RTIF (bit 6) of TFLG2 by
writing a 1 in it
• (3) enable RTI interrupt, so we set the RTII bit (bit 6) of TMSK2
to 1 © 2016, Macam, Introduction to Microcomputers 33
• Solution:
– Also, the real-time interrupt vector starting
address should be pointed to by a JMP instruction
placed at $00EB
– This routine must clear the RTIF flag before it
returns.
– The following program meets our objectives:

For longer delays, it is advised that a

higher RTI rate be used in order to
minimize the number of interrupts to
the main program

Port A: Simple Mode of Operation
• Pins PA0 – PA2 are input only
• Pins P3 – PA6 are output only
• Pin PA7 can be configured for input or output
• Port A has two modes of operation:
– Simple Parallel I/O mode
– Timer-system related mode

• Simple parallel I/O mode
– Pins PA0 – PA2 general digital input pins
– E.g., EVBplus2: PA0 connected to a push button
switch
– When jumpers J17 on the EVBplus2 are moved to
the lower position (labeled with PA26) pin PA6
drives the on-board Infra-Red (IR) transmitter, and
PA2 receives data from the IR receiver

• Pins PA3 – PA6 can serve as general output
pins in the simple mode
• EVBplus2 : on-board speaker connects to PA5
• No configuration needed for PA0 – PA6 in the
simple mode (i.e., after RESET Port A’s default
mode is simple I/O mode)
• Pin PA7:function as either input or output
– Requires a data direction register (DDR)
– Bit 7 of PACTL, a register at $1026 (direction bit)

• The EVBplus2
– 8-input powered sensor port (see figure below)
– Up to four digital sensors can connect to this port
at PA0, PA1, PA2 and PA7 (when used for simple
parallel input)
– 100Kohm pull-up resistor on each sensor input
– I.e., PA0 – PA2 & PA7 =1 if no input is connected

68HC11: Input Capture Function
• Saves the main timer value into a 16-bit
register when the rising (or falling) edge of a
signal arrives
• This enables the measuring of the width or
period of an unknown signal & time reference
to trigger other operations
• The 68HC11 has three input-capture functions
– Each function has its own input-capture register

• When used in the timer mode:
– Pins PA0 – PA2: Connected to one of the 3 input
capture registers in the 68HC11
– The 16 bit input capture registers TIC1 ($1010-$1011),
TIC2 ($1012-$1013) & TIC3 ($1014-$1015)
• Not affected by RESET & cannot be written by program
– Associated with pins PA2, PA1 & PA0, respectively
– They make a capture when an edge occurs on one of
these input pins
– When capture is made, the time of the capture (input
capture) is copied from the TCNT register into the input
capture register
68HC11: Input Capture Function Registers

• Controlled by the edge bits in TCTL2 ($1021)
– Contains three pairs of edge bits, one pair for each
capture register
– The pair EDGxB & EDGxA : edge control bits
associated with the TICx register and its PA(3-x)
input pin (where x = 1, 2, or 3)
– E.g., EDG3B & EDG3A: edge bits for TIC3/PA0

• The function of the edge bits:
• If both edge control bits for a given capture register

are 0, the capture is disabled; there is never a
capture and the corresponding Port A pin acts as a
simple input pin
– This is the situation after RESET, since the TCTL2 register
content upon RESET is $00

68HC11: Input Capture Function Example
• Time of a falling edge on pin PA2 must be
detected. How much TCTL2 be set up to do this?
Assume: PA1 & PA0 (in simple I/O mode)
• Solution:
– PA2 is connected to TIC1 (input capture register 1)
– (The table saw before) shows that for a falling edge we
must set EDG1B and EDG1A to 1 and 0, respectively
– For PA0 and PA1 to operate in the simple I/O mode,
their edge bits must be zero
– Therefore, TCTL2 must be loaded with %00100000 =
$20. Thus the code
68HC11: Input Capture Function Example
• Solution:
– The code:
– LDAA #$20
STAA $1021
Will set up TCTL2 to capture the time of a falling

edge on PA2

• Summary (For your reading pleasure):
– In the timer mode the three input pins PA2 – PA0
of Port A ($1000) can be connected to external
devices
• Allows the 68HC11 to capture the free-running timer
(TCNT) count in 16-bit registers (TIC1, TCI2 and TIC3 at
addresses $1010-$1011, $1012-$1013 and $1014-
$1015, respectively) upon a signal from the external
device(s)
• The signal could be a rising edge, a falling edge or a
pulse as determined by the edge bits of the TCTL2
register ($1021)
68HC11: Input Flags & Interrupts
• In the timer mode (For your reading pleasure):
– The 68HC11 allows the PA0 – PA2 lines to interrupt
– Two new registers are of interest here: The Timer
Interrupt Mask 1 (TMSK1) and the Timer Interrupt
Flag 1 (TFLG1) registers located at $1022 and
$1023, respectively
– These registers are cleared after RESET

Interrupt bits
Flag bits

• Bits 2, 1, and 0 of the TFLG1 register signals an
input capture on registers TIC1, TIC2 and TIC3,
respectively
• If a capture is made, the flag will be set to 1
• The flag can be cleared by writing a 1 into its
bit position
• These flags are 0 after RESET

• Input capture occurs every time a selected
edge is detected on the corresponding timer
input pin, even if the corresponding input-
capture flag is already set
– The value read from the input-capture register
corresponds to the most recent edge at the pin,
which may not be the edge that caused the input
capture flag to be set

• Each flag bit has a corresponding interrupt
mask bit in TMSK1
– i.e., bit ICxF in TFLG1 has bit ICxI as its
corresponding mask in TMSK1, x = 1, 2, 3
– If this bit is set, a capture will cause an interrupt in
accordance to the following table

• The ICxI control bit allows the user to configure
each input-capture function for polled or
interrupt-driven operation but does not affect the
setting or clearing of the corresponding ICxF bit
• When ICxI is zero, the corresponding input
capture interrupt is inhibited, and the input
capture is operating in a polled mode
– In this mode, the ICxF bit must be polled (read) by
user software to determine when an edge has been
detected

• When the ICxI bit is 1, a hardware interrupt
request is generated whenever the
corresponding ICxF bit is set to 1
• Before leaving the interrupt service routine,
software must clear the ICxF bit by writing 1s
to the TFLG1 register

68HC11: Measuring Pulse Widths
• Using two input capture registers
– Pulse input: connected to both pins PA0 & PA1
• or input capture registers TIC3 and TIC2, respectively

Input Flags & Interrupts: Program Example
• A program to measure pulse widths

– The pulse is assumed to be positive
– Uses capture register TIC2 to determine the time
of the positive, or leading, edge of the pulse and
capture register TIC3 to find the negative or
trailing edge
– The difference between the times is the pulse
width (saved at $C000)

• This program does not use interrupts

– Operates in a polled mode
– Works for pulses < 32.77 ms
– Use TOF for longer pulses
– Misses very small width pulses (few µs)
– Falling edge (earliest place) occur & be properly
handled is after: STAA TFLG1,X instruction

• Input: A square wave generator @
10 KHz
• Time difference (in E clock cycles) ?
• Solution:
– A 10 KHz (T = 100ms = 200 E
cycles) wave produces a pulse
that is high for 50 µs
– This corresponds to 50 µs/0.5
µs = 100 E clock cycles
– Difference in counts should be
100 (decimal) = $64

Input Flags & Interrupts: Program Example 3
• A positive pulse arrives at pin PA0

• Use input-capture polled operation to
determine the pulse width
• Solution:
– Port A input pin (PA0) : two consecutive captures:
• 1) on a rising edge & 2) on a falling edge
• PA0 edge bit: reconfigured for a falling edge
immediately after input capture at the rising edge


• Test this using the simulator

• Use a “Connection with Switch” element to
configure

• When the switch is closed PA0 = 0
• When the switch is open, pin PA0 receives a 1
• Start the switch in the closed position, run the
program and quickly open the switch and then
close it (by double clicking it two times)
• This action produces a positive pulse at PA0
• You may also step through the program and
watch the “timer” registers and register D

• NOTE:
– When you run a program that terminates with a
SWI on the simulator, you can replace SWI with
the “loop in place” instruction “BRA *”
– The SWI is a software interrupt that attempts to
run a routine whose default starting address
($FFFF) is stored at $FFF6, $FFF7

• NOTE:
– Edit locations $FFF6 and $FFF7 and write the two
bytes $C0 and $04 in those locations, respectively
– This results in a program that keeps re-running
itself if the program actually starts at $C004
– Alternatively, for the above program, you may
append it with the following code:
ORG $FFF6
FCB $C0,$04

68HC11: Output Compare Function
• Compares the value of the main timer with
that of an output compare register once every
E clock cycle
– Used to create a delay or generate a digital
waveform with a specified frequency and duty
cycle
– E.g., to control the position of a servo motor. See
assignment Problem 17

• Primary usage:
– Make a copy of the main timer, add a delay to this
copy, and then save this sum (using a double-byte
instruction such as STD) into an output-compare
register
• The added delay determines when the value of the
main timer will be equal to that of the output-compare
register
• Five output-compare functions
– Each function has a 16-bit compare register

68HC11: Output Compare Registers

• The output compare registers
– Signal the 68HC11 that an event has occurred
– Can control the level on output pins PA3 – PA7
– labeled TOC1 (Timer Output Compare 1) to TOC5
and occupy locations $1016 through $101F
– When time in TCNT = the number in one of those
registers: A compare has occurred and a flag will be set
– Each output compare register will have its flag set
once every 32.77 ms when TCNT equals the
number in the register
– Upon RESET, each TOCx register contains $FFFF
Interrupt bits
Reserved for output compare Reserved for input

function (Upper five bits) capture function (lower three bits)
Flag bits
• When the number in the TOC register equals the
number in TCNT
– The flag will set in TFLG1
– This could in turn (settings of register TCTL1) affect
the logic level at the Port A pin associated with that
particular output compare
– If the corresponding bit is set in TMSK1, a compare
will cause an interrupt
– Upon RESET, the TMSK1 register is reset to $00
– Therefore, output compare interrupts are disabled upon RESET
– Have to set the desired bits in TMSK1 to allow output compare
interrupts

• The output compare interrupt vectors,
associated Port A pins and interrupt masks

Output Compare Function Example
• The EVBplus2 has just been turned on and no
signals are connected to Port A pins
• What should be in TFLG1 immediately after
power is turned on? After 50 ms?
• Solution:
– Upon RESET, TFLG1 has $00 content
• Because no inputs are connected, no edges will be
detected by the input capture registers
• Therefore no input capture flags will be set and TFLG1
bits 0, 1 and 2 will remain 0

Output Compare Function Example
• Solution:
– The output compare registers, however, set their flags
(OC1F – OC5F) after 32.77 ms
• This happens because the TOCx registers contain $FFFF
upon RESET
• The first output compare occurs when TCNT reaches $FFFF
(this takes 32.77 ms after RESET
• Therefore, TFLG1 will contain $00 just after reset, and
%11111000 = $F8 after 32.77 ms.
• Verify at THRSim11, watch TCNT and TFLG1
contents while running a simple program (E.g.,
loop “BRA *”)
Programming Example 4
• Write a program that uses output compare
interrupts 15 ms after execution starts. The
interrupt service routine should start at $C100
• The service routine should turn Port B LEDs
and disable further output compare interrupts
before it returns.
• The program should also verify the 15 ms
delay

Programming Example: Solution
Solution: OC5 will be used. The program might be:

Programming Example
• Prior to entering the interrupt service routine
– A JMP to $C100 must be written into locations
$00D3 - $00D5 (the EVBplus2 pseudo-vector for
OC5)
– and a CLI must be issued
– The program simply finds the current value in
TCNT and adds 30,000 (decimal) counts to it
– It then clears the flag and sets the mask to allow
interrupts

Programming Example
• Prior to entering the interrupt service routine
– The flag must be cleared before the OC5I interrupt
bit is set, or it will interrupt immediately
– At the end of the program, location $C000 (VALUE)
contents should reflect (approximately) the 15 ms
delay that corresponds to 30,000 E-cycles or
$7530

Programming Example
• Can run on THRSim11, but change to following
• Replace SWI and the three instructions
preceding it by BRA *
– Replace
ORG $00D3
JMP $C100
– By
ORG $FFE0
FDB $C100
Control of Port A Output Pins
• Timer output compare registers 2 to 5 (TOC2 –
TOC5) operate in the same way
• Output compare register 1 acts differently (it
will not be considered here)
• TOC2 to TOC5 control pins PA6 through PA3,
respectively, in accordance with the bit
settings in the Timer Control 1 (TCTL1) register
at $1020 (Refer to figure and table below)


• TCTL1 contains four pairs of bits (OMx/OLx, x =
2, 3, 4, 5) that control these output pins
• If the setting for a pair of these bits is 00, the
associated pin is disconnected from the
output compare register and can be used for
general-purpose (simple) output
• This is the default configuration upon RESET
• Here, pins PA3 – PA6 are output only and
operate in simple I/O
• Pin PA7 is input or output and is controlled by
bit 7 (data direction bit) in the PACTL register
($1026)
• The three other bit combinations of OMx/OLx
allow the user to toggle, set or clear the
corresponding pins on each comparison.

• Generate a 1000 Hz positive square wave on pin
PA6
• Employ the 68HC11 output compare function in
polling mode (i.e., check for OC2F flag set)
• Solution:
– A 1000 Hz positive square wave is a pulse train of 0.5
ms duration positive pulse followed by a 0.5 ms zero
signal
– PA6 is associated with the OC2F flag and the
associated output compare register TOC2 (at $1018)
can handle this problem very nicely
• The program is shown later
• It clears the OC2F flag and waits for it to set
• OCF2 =1, when TCNT = the number in TOC2
• The equivalent of 0.5 ms, 1000 counts, is then
added to the value in TCO2 & program repeats
• Each time the flag sets the output toggles,
producing the required square wave
• Pin PA6 will toggle if it is configured so that
OM2 and OL2 are equal to 0 and 1,
respectively, I.e., if the contents of TCTL1 is $40
Programming Example 5: Solution
THRSim11: Generates a transient wave that settles into a 1000

Hz wave. Test this program use the virtual bit oscilloscope to
display the generated wave (wait couple minutes to see any
signal activity)
68HC11: Pulse Accumulator
By default, it is $00 Pin PA7 is controlled
(configured for input)
Data direction register by this register
if = 1, then it is outward
Port A Control (PACTL) @ $1026

DDRA7 PAEN PAMOD PEDGE DDRA3 I4/O5 RTR1 RTR0
If =0, pulse accumulator

disabled. If 1, Can be configured for more
accumulator enabled advanced use as an input to the
After RESET, PA7 can be 68HC11 pulse accumulator
used for simple input

This register can be written 8-Bit pulse
by the program accumulator
Port A Count (PACNT) $1027

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pulse accumulator functions based on what bits on PACTL register is set

• Two uses of PA7 on input
– If PAEN = 0 (upon RESET)
• The pulse accumulator is disabled
• PA7 used as a general purpose input pin
– If PAEN =1
• The pulse accumulator is enabled
• If PAMOD bit in PACTL = 0
– The pulse accumulator is in an external event
counting mode

• If PAMOD bit in PACTL = 0
– If PEDGE = 1
• Pulse accumulator will respond to the positive edge on
the PA7 pin
• Pulse accumulator will increment PACNT
– If PEDGE = 0
• Pulse accumulator will respond to the negative edge on
the PA7 pin
• Pulse accumulator will increment PACNT
– PA7 acts as the pulse accumulator input (PAI)

68HC11: Pulse Accumulator Example
Assume $40 is stored in the PACTL register at $1026 memory location
$40 = 0100 0000
PACTL ($1026)
7 1 1 Bit 4 1 Bit 2 Bit 1 Bit 0
PAEN is set and PEDGE is unset. Pulse accumulator is

enabled and counts the number of external pulses arriving at
PA7, triggered on the falling edge

Assume $50 is stored in the PACTL register at $1026 memory location
$50 = 0101 0000
PACTL ($1026)
7 1 1 1 1 Bit 2 Bit 1 Bit 0
PAEN is set and PEDGE is set. Pulse accumulator is enabled

and counts the number of external pulses arriving at PA7, triggered
on the rising edge

Write a program to test the pulse accumulator in the THRSim11
Solution: This program assumes a switch is connected to PA7. Every time the
switch is closed and then opened (a pulse is applied at PA7), Port B LEDs will
display the contents of the pulse accumulator. The program configures PACTL so
that PACNT increments on a falling edge.
PORTB EQU $1004
PACTL EQU $1026
PACNT EQU $1027
ORG $C000
LDAA #$40
STAA PACTL
CLR PACNT
CLR PORTB
GO LDAA PACNT
STAA PORTB
BRA GO
• The pulse accumulator (PA)
– Associated with two flags in the TFLG2 register
• PAIF (Pulse Accumulator Input Flag)
– Is set whenever the PA is active and a selected edge on PA7 is
detected.
• The PAOVF (Pulse Accumulator Overflow Flag)
– Is set whenever the count in PACNT rolls over from $FF to $00
• both flags are cleared by writing 1s into their bit
positions in TFLG2

• In TMSK2 register: PAII & PAOVI bits
– Are the corresponding interrupt enable bits
• If set, the 68HC11 will interrupt whenever the
corresponding flag is set
• if the I bit in CCR = 0 the interrupt will be served by
running its interrupt routine
– EVBplus2: The PAII interrupt vector
• Is at $FFDA and $FFDB, and its pseudo-vector @ $00CA -
$00CC
– EVBplus2: The PAOVI vector
• Is at $FFDC and $FFDD, and its pseudo-vector is at $00CD
- $00CF

• A debounced switch (or a pulse generator
output) is connected to PA7
• It must display $FF on Port B after five switch
throws
• Write a program to do this employing the
68HC11 pulse accumulator’s overflow
interrupt feature.

68HC11: Pulse Accumulator Example: Solution
1. The SP must be positioned.
2. The starting address of the interrupt routine must
be selected and a JMP to it entered into $00CD -
$00CF. The routine then stores $FF at $1004
3. PACTL must be set up to enable the pulse
accumulator in the external event counting mode
4. The PAOVF flag must be cleared and the PAOVI bit
must be set to enable interrupts upon pulse
accumulator overflow
5. The number – 5 decimal (or $FB) can now be
written to the PACNT register
68HC11: Pulse Accumulator Example: Solution
• After five switch throws the pulse accumulator
should overflow and interrupt
• Obviously, we could have used PA7 in simple input
mode in a program that polls PA7 and increments a
variable count (maintained in a memory location)
every time PA7 goes high
• And once the count reaches 5, $FF is saved in $1004
• However, this approach keeps the processor very
busy with the polling of PA7
• The interrupt approach is much more efficient

ECE3620Unit 8

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ECE 3620

© 2016, Macam S Dattathreya, PhD

6 Parallel I/O – Ports B and C 1

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The Timing System and Port A

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Crystal Oscillator: Creates an electrical signal with

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Timer Counter (TCNT) Register (16-Bit)

• Example: Assume TCNT = $01FB before executing

Execute the instruction LDD $100E (Requires 5 cycles to read)

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Execute the instruction LDAA $100E (Requires 4 cycles to read)

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Reads TCNT register

Reads TCNT register

What is wrong with this program?

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Problem#2: 16-bit addition limitation. Overflow may occur (for other

Problem#3: Longest delay in this approach: 32.77 ms. HC11 will be

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• This program generates a square wave

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For longer delays, it is advised that a

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• If both edge control bits for a given capture register

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Will set up TCTL2 to capture the time of a falling

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