SCAN & EDT

Compression with Tessent

 Contents
• Embedded deterministic test
– Block diagram
• Decompressor
• compactor
– Functionality
• Operational waveform & controls
– EDT IP generation
• Generation of IP without design
• Generation IP with the design
– Synthesis & scan insertion with EDT
• Requirements & constraints
WhatEmbedded
is EDT? & Whydeterministic
EDT? test
• EDT(Embedded deterministic test) means extra circuitry embedded to IC
and generates deterministic patterns to detect faults in circuit.

• Tessent TestKompress achieves compression of scan test data by

controlling a large number of internal scan chains using a small number of
scan channels.
• EDT extends ATPG with improved compression with reduction in test time.
• EDT technology is based on traditional, deterministic ATPG and uses the
same fault models to obtain similar test coverage using a familiar flow.
Introduction

Block Diagram of EDT

External flow

Internal flow
Decompressor
• The decompressor resides between the
channel inputs and the scan chain inputs
of the core.
• Decompressor will take the seed from the
ATE and decompresses the seed by giving
it to the LFSM
• The decompressor consists of a LFSM
which will provide the random sequence
patterns
• These random sequence are given to the
scan chains through phase shifters
• The phase shifter will allow change the bit
of the sequence through XOR gates to
have two different chains
 Compactor
• Compacts the test responses from the scan chains in your core design into a small number of scan output
channels as they are shifted out
• The compactor resides between the core scan chain outputs and the channel outputs connected to the
tester
• It primarily consists of XOR gates
EDT Controller
• EDT logic to load capture, and/or
unload values on a specified scan
chains by inserting custom logic
between the scan chain outputs and
the compactor/decompressor.
• The custom logic (masking) allows
you to either feed the desired circuit
response (0/1) to the compactor or tie
the scan chain output to an unknown
value x.
Functionality of EDT

• The seed values from the ATE is given as a input to the decompressor through the
EDT channels
• The seed values are given to the LFSM which are present in the decompressor
which would provide a sequence of patterns to the Phase shifters
• The Phase shifters allows to have randomness in the sequence that are given from
LFSM
• These random sequence are given to the input of scan chain and the output of the
scan chain is given to the compactor
• The compactor performs XOR operations on the patterns received and gives the
compressed patterns to the EDT channel out
• The ATE compares the received compressed patterns from the EDT and verifies
for any error
• By default, Bypass circuitry is included in the EDT logic. The bypass circuitry
allows you to bypass the EDT logic and accessed uncompressed scan chains in
the design core.
Operational waveform
• Operational Waveform

Mandatory Controls Optional Controls

Edt_bypass
Edt_reset
EDT IP
GENERATION
 EDT IP Generation
• Pre Synthesis Flow

Requirements:-
To Create the EDT logic during RTL
stage, we must below requirements in
our design.
• Number of external scan channels.
• Number of internal scan chains.
• Longest scan chain length range:
 Pre synthesis - Sample Script
#set the context
set_context dft -rtl
#Interface
set int [get_config_element interface \
#output directory -in /$spec/EDT/controller(c1)]
set_tsdb_output_directory ../outputs/tsdb_out_two_counter_rtl_edtmodes_all foreach {prop val} {edt_clock edt_clock edt_update edt_update edt_channels_in_bus edt_channels_in
read the files edt_channels_out_bus edt_channels_out} {
read_verilog ../design/counter_top.v set_config_val $prop -in $int $val }
read_verilog ../design/period_3.v set int [get_config_element StaticExternalControls \
read_verilog ../design/two_counter.v -in /$spec/EDT/controller(c1)/interface]
#read cell library foreach {prop val} {edt_bypass edt_bypass edt_single_bypass_chain edt_single_bypass_chain} {
read_cell_library ../library/dti_tm28hpc_l30_stdcells_rev0p3p0.atpg set_config_val $prop -in $int $val }
#set the current design #Bypass chains
set_current_design counter_top set int [get_config_el BypassChains \
#design level -in /$spec/EDT/controller(c1)]
set_design_level physical_block foreach {prop val} {present on bypass_chain_count 2 single_bypass_chain on} {
#Adding DFT signals set_config_val $prop -in $int $val }
add_dft_signals test_clock scan_en edt_update -source_nodes {scan_clk scan_enable_i edt_update} #compactor
add_dft_signals edt_clock shift_capture_clock -create_from_other_signals set int [get_config_element compactor \
#For adding EDT modes -in /$spec/EDT/controller(c1)]
add_dft_signals edt_mode
foreach {prop val} {type xpress} {
add_black_boxes -auto
check_design_rules set_config_val $prop -in $int $val }
# Configuring the EDT Spec stop
set spec [create_dft_specification -sri_sib_list {occ EDT}] #display specification add the below configurations
add_config_element $spec/EDT set int [get_config_el EdtChannelsIn(1) \
#connections -in /$spec/EDT/controller(c1)/Connections]
set int [get_config_el Connections \ foreach {prop val} {port_pin_name edt_channels_in1} {
-in /$spec/EDT] set_config_val $prop -in $int $val }
foreach {prop val} {edt_update edt_update} { set int [get_config_el EdtChannelsIn(2) \
set_config_val $prop -in $int $val } -in /$spec/EDT/controller(c1)/Connections]
set int [get_config_el StaticExternalControls \ foreach {prop val} {port_pin_name edt_channels_in2} {
-in /$spec/EDT/Connections] set_config_val $prop -in $int $val }
foreach {prop val} {edt_bypass edt_bypass edt_single_bypass_chain edt_single_bypass_chain} {
set int [get_config_el EdtChannelsOut(1) \
set_config_val $prop -in $int $val }
#Controller -in /$spec/EDT/controller(c1)/Connections]
add_config_element $spec/EDT/controller(c1) foreach {prop val} {port_pin_name edt_channels_out1} {
set int [get_config_el controller(c1) \ set_config_val $prop -in $int $val }
-in /$spec/EDT] set int [get_config_el EdtChannelsOut(2) \
foreach {prop val} {longest_chain_range {150 160} scan_chain_count 100 input_channel_count 2 -in /$spec/EDT/controller(c1)/Connections]
output_channel_count 2 } { foreach {prop val} {port_pin_name edt_channels_out2} {
set_config_val $prop -in $int $val } set_config_val $prop -in $int $val }
 Pre synthesis - Sample Script( cont.)

#OCC Specifications #occ_clk2

set_config_value $spec/reuse_modules_when_possible -in $spec off add_config_element $spec/occ/controller(occ_clk2)
set_config_value $spec/use_rtl_cells -in $spec on set int [get_config_el controller(occ_clk2) \
set_config_value $spec/use_rtl_synchronizer_cell -in $spec on -in /$spec/occ]
set_config_value $spec/use_synchronizer_cell_with_reset -in $spec on foreach {prop val} {clock_intercept_node /u_two_counter/clk2 capture_window_size 10 type standard
add_config_element $spec/occ leaf_instance_name occ_ctrl } {
set_config_value $spec/occ/capture_window_size -in $spec 10 set_config_val /$spec/occ/controller(occ_clk2)/$prop -in $int $val }
set_config_value $spec/occ/static_clock_control -in $spec external set int [get_config_el Connections \
set_config_value $spec/occ/type -in $spec standard -in /$spec/occ/controller(occ_clk2)]
set_config_value $spec/occ/shift_only_mode -in $spec on foreach {prop val} {scan_en scan_enable_i fast_clock /u_pll_t2/clk_b } {
set_config_value $spec/occ/leaf_instance_name -in $spec occ_ctrl set_config_val $prop -in $int $val }
#interface
et int [get_config_el Interface \ #occ_clk3
-in /$spec/occ] add_config_element $spec/occ/controller(occ_clk3)
foreach {prop val} {scan_en scan_enable_i} { set int [get_config_el controller(occ_clk3) \
set_config_val $prop -in $int $val } -in /$spec/occ]
#connections foreach {prop val} {clock_intercept_node /u_two_counter/clk3 capture_window_size 10 type standard
set int [get_config_el Connections \ leaf_instance_name occ_ctrl } {
-in /$spec/occ] set_config_val /$spec/occ/controller(occ_clk3)/$prop -in $int $val }
foreach {prop val} {scan_en scan_enable_i} { set int [get_config_el Connections \
set_config_val $prop -in $int $val } -in /$spec/occ/controller(occ_clk3)]
set int [get_config_el StaticExternalControls \ foreach {prop val} {scan_en scan_enable_i fast_clock /u_pll_t2/clk_c } {
-in /$spec/occ/Connections] set_config_val $prop -in $int $val }
foreach {prop val} {test_mode scan_mode_i fast_capture_mode fast_capture_mode
static_clock_control_mode static_clock_control_mode shift_only_mode shift_only_mode } { report_config_data > ../reports/edtoccsib_counter_edtmode.spec
set_config_val $prop -in $int $val } process_dft_specification -validate_only
#controller process_dft_specification
#occ_clk1 extract_icl
add_config_element $spec/occ/controller(occ_clk1)
set int [get_config_el controller(occ_clk1) \
-in /$spec/occ]
foreach {prop val} {clock_intercept_node /u_two_counter/clk1 capture_window_size 10 type
standard leaf_instance_name occ_ctrl } {
set_config_val /$spec/occ/controller(occ_clk1)/$prop -in $int $val }
set int [get_config_el Connections \
-in /$spec/occ/controller(occ_clk1)]
foreach {prop val} {scan_en scan_enable_i fast_clock /u_pll_t2/clk_a } {
set_config_val $prop -in $int $val }
Collateral files generated Pre-synthesis flow

-->dft_inserted_design --> instruments

EDT IP Generation
• Post Synthesis Flow
Post Synthesis Flow Sample script:
#settting contest to EDT
set_context dft -edt
#setting the output directory
set_tsdb_output_directory ../outputs/tsdb_out_edtdftsignal
#reading the library
read_cell_library ../library/dti_tm28hpc_l30_stdcells_rev0p3p0.atpg
#reading the scan inserted netlist
read_verilog ../design/counter_top.vg
#setting current design to top module
set_current_design counter_top
#adding clocks
add_clocks 0 scan_clk
add_clocks 1 rst_n
add_clocks 0 occ_ctrl/fast_clock -internal -pulse_always
add_clocks 0 occ_ctrl_1/fast_clock -internal -pulse_always
add_clocks 0 occ_ctrl_2/fast_clock -internal -pulse_always
#adding constraints
add_input_constraints -c1 scan_mode_i
add_input_constraints -c0 static_clock_control_mode
#adding scan chain group information
add_scan_groups grp1 ../design/occ_scan_tied_setup.testproc
add_scan_chains chain0 grp1 {ts_si[0]} {ts_so[0]}
add_scan_chains chain1 grp1 {ts_si[1]} {ts_so[1]}
add_scan_chains chain2 grp1 {ts_si[2]} {ts_so[2]}
add_scan_chains chain3 grp1 {ts_si[3]} {ts_so[3]}
#setting edt channel
set_edt_options -channel 1
add_black_boxes -auto
#Drc checking
check_design_rules
report_edt_configurations -verbose > ../reports/edt_configurations.rpt
#write_edt_files ../outputs/edt_files.v -verilog -replace
write_edt_files ../outputs/edtip_files -verilog -replace
#create_patterns
report_statistics > ../reports/edt_statistics.rpt
report_scan_volume > ../reports/edt_scanvolume.rpt
Collateral Files: Post Synthesis flow