Block diagram &

Internal Architecture
Internal architecture of 8051
 Internal architecture of 8051
 It consists of
 8 bit ALU, with two registers A & B
 16 bit Program Counter & Data Pointer
 8 bit Program Status Word
 8bit Stack Pointer
 128 bytes Internal RAM
 4 register banks, each containing 8 registers.
 16 bytes, which may be addressed at bit level.
 80 bytes of gent purpose data memory.
 Internal ROM / EPROM / Flash memory of 4KB
 Can be extended separate 64KB address space for data & code memory.
 32 discrete I/O pins, grouped as four 8 bit ports.
 Full Duplex UART.
 Two l6 bit timer / counter - T0 & T1
 Two external & three internal interrupt sources
 Control registers –TCON, TMOD, SCON, PCON, and IP & IE
 Oscillator & clock circuits
 Introduction
 The 8051 is the original member of the MCS-51family, and is the
core for all MCS-51 devices. The features of the 8051 core are:
 8-bit CPU optimized for control applications
 Extensive Boolean processing (single-bit logic) capabilities
 64K program memory address space
 64K data memory address space
 4K bytes of on-chip program memory
 128 bytes of on-chip data RAM
 32bidirectional and individually addressable I/O lines
 Two 16- bit timer/counters
 Full duplex UART
 6- source / 5 vector interrupt structure with two priority levels
 On-chip clock oscillator
The basic architectural structure of this 8051 core is shown below.
 The programming model of 8051 is a collection of 8 bit
and 16 bit registers and 8 bit memory locations.
 Registers:
 8051 has 34 general purpose or working registers.
Two of them A & B, hold results of many instructions,
particularly Mathematical and logical operations, of
8051 CPU.
 The other 32 Reg. arranged as a part of internal RAM
in four banks RBO-RB3.
 A (Accumulator) register is used for many operations -
Addition,
 Reg. B is used with Reg.A for multiplication & division
operations and also for data transfer.
 Subtraction, integer- multiplication & division and
Boolean bit manipulations.
 CY AC FO RSI RSO OV - P
 Carry out Auxiliary General Register Banks Over flow Parity of
From carry for purpose RB0-RB3 flag Accumulator
MSB of BCD set by
ALU operations hardware to 1
Operand if it contains odd
number
of ones

 Note: The contents of (RS1-RS0) enable the working register banks as follows
(0, 0) - Bank 0 (00H-07H)
(0, 1) - Bank 1 (08H-0FH)
(1, 0) - Bank 2 (10H-17H)
(1, 1) - Bank 3 (18H-1FH)
 Carry flag is set whenever there is carry out from MSB. This flag is
after 8 bit ADD/ SUB operation.
 It can also be set to 1 or 0 directly using SETB C or CLR C.
 Auxiliary carry: If there is a carry from D3 to D4 position during
Add/sub operation, this bit will set. Otherwise, it is cleared. This flag
is used for BCD operations.

 Parity Flag reflects the number of 1’s in ‘A’. If ‘A’ contains an odd
number of 1’s, then P=1. Therefore P=0, if A has an even number of
1’s.
 Over Flow Flag: This flag is set whenever the result of a signed
number operation is too large to be accommodated in 7bits, causing
the Higher order bit to over flow into the Sign Bit.
 8051 Oscillator & Clock
 8051 has on Chip Oscillator but needs an external clock to run it. A Quartz
crystal
 oscillator is connected to XTAL2 & XTAL1. C1 &C2 are also connected as
shown above.
 C1= C2= 30pf (typical)
 xtal oscillator =1 to 16 MHz.

 Each Machine Cycle is made up of 6 states. A state is basic time interval for
discrete operations of µcontroller such as Opcode fetch, decode an opcode,
Execute an opcode.Two oscillator pulses define a state.
 Program Instructions may require 1/2/3/4 machine cycles, depending on its
type.
 RST
 It is an input and is active High (Normally Low) by applying
a High pulse to this pin, µc will be reset and terminate all
activities.
 On reset PC - 0000
 ACC - 0000
 B - 0000
 PSW - 0000
 SR - 0007
 DPTR-0000


 EA - External Access (of Memory)

 PSE - Program Store Enable
 ALE - Address Latch Enable.
WHAT DO THE SFRs CONTAIN JUST AFTER POWER-ON OR A RESET
 The following table lists the contents of each SFR after power-on or a hardware
reset Register Value in Binary
*ACC 0000 0000
*B 0000 0000
*PSW 0000 0000
SP 0000 0111
DPTR 0000 0000
DPH 0000 0000
DPL 1111 1111
*P0 1111 1111
*P1 1111 1111
*P2 1111 1111
*P3 8051 XXX00000
*IP 8052 XX000000
*IE 8051 0XX00000
TMOD 8052 0X000000
*TCON 0000 0000
*+T2CON 0000 0000
TH0 0000 0000
TL0 0000 0000
TH1 0000 0000
TL1 0000 0000
+TH2 0000 0000
+TL2 0000 0000
+RCAP2H 0000 0000
+RCAP2L 0000 0000
*SCON 0000 0000
SBUF 0000 0000
PCON Indeterminate
HMOS 0XXXXXXX
CHMOS 0XXX0000
 Memory organization
 8051 has separate address spaces for program memory
and data memory.
 Program memory can be up to 64KB, lower 4KB may
reside ON-CHIP.
 8051 can address up to 64KB of data memory.
 It has 128bytes of ON-CHIP RAM and SFR (128B).
 The lower 128bytes can be accessed either by direct
addressing or indirect addressing.
F8 FF

F0 B F7

E8 EF

E0 ACC E7

D8 DF

D0 PSW D7

C8 T2CON RCAP2L RCAP2H TL2 TH2 CF

C0 C7

B8 IP BF

B0 P3 B7

A8 IE AF

A0 P2 A7

98 SCON SBUF 9F

90 P1 97

88 TCON TMOD TL0 TL1 TH0 TH1 8F

80 P0 SP DPL DPH PCON 87

 Special Function Registers

Symbol Name Address

*ACC Accumulator 0E0H
*B B register 0F0H
*PSW Program Status Word 0D0H
SP Stack Pointer 81H
DPTR Data Pointer 2 Bytes 82H
DPH Low Byte 83H
DPL High Byte 80H
*P0 Port 0 90H
*P1 Port 1 0A0H
*P2 Port 2 0B0H
*P3 Port 3 0B8H
*IP Interrupt Priority Control 0A8H
*IE Interrupt Enable Control 89H
TMOD Timer/Counter Mode Control 88H
*TCON Timer/Counter Control 0C8H
*+T2CON Timer/Counter 2 Control 8CH
TH0 Timer/Counter 0 High Byte 8AH
TL0 Timer/Counter 0 Low Byte 8DH
TH1 Timer/Counter 1 High Byte 8BH
TL1 Timer/Counter 1 Low Byte 0CDH
+TH2 Timer/Counter 2 High Byte 0CCH
+TL2 Timer/Counter 2 Low Byte 0CBH
+RCAP2H T/C 2 Capture Reg. High Byte 0CAH
+RCAP2L T/C 2 Capture Reg. Low Byte 98H
*SCON Serial Control 90H
SBUF Serial Data Buffer 87H
PCON Power Control
 RBO-RB3: 32Bytes are kept aside for register Banks, of four. In each Bank, R0-R7
(8) registers are present

 Though 4banks of register are kept aside, micro controller at a time can access only
one register bank, where as other register banks will be used as simple RAM
locations.
 By default RB0 is selected, on power ON.
 We can switch to other banks, by using D4 & D3 bits of PSW.
 State the contents of RAM locations after the following program.
 SetB PSW4 select bank 2
 Mov R0, #99h
 Mov R1, #85h
 Mov R2, #3Fh.
 PC can access the memory from 0000H –FFFFH. Program address higher than
0FFFH, which exceed the internal ROM capacity will cause 8051