PLACEMENT

 placement is the process of finding the suitable physical location for each standard cell in the design
standard cells are placed on placement tracks with automatically at placement stage
Steps:
1. Pre Placement
2. Initial Placement / Course Placement / Global Placement
3. Legalization
4. HFNS (High Fanout Net Synthesis)
5. Iteration for Congestion, Timing, DRV, and Power Optimization
6. Timing optimization iterations
7. Scan-Chain Reorder
 PLACEMENT

Goals of Placement:
1. Timing,area,and power optimization
2 . Routable Design
3 . Min.cell density ,pin density (Reduce the congestion due to cells and pins)
4. Minimum timing DRC’s
Inputs To Placement Stage:
1. Netlist
2. Mapped and Floor planed Design
3. Logical and Physical Libraries
4. Design Constraints
PLACEMENT STAGES
1. Pre Placement:
 Before starting the actual placement of the
standard cells present in the synthesized netlist, we
need to place various physical only cells like end-
cap cells, well-tap cells, IO buffers, antenna diodes,
and spare cells
 Once the pre Placement stage has been
completed, We can start the placement of standard
cells
 but before that, we have to provide all the correct
placement and optimization settings that we want
to be applied while the tool does the placement and
optimization.
 PLACEMENT STAGES

2.Global placement/Coarse placement:

 The std cells can be placed into the core region
 cells are overlapped , cells does not have legalized locations
 it is rough placement

3 Legalization :
 The global placement stage, the instances are left with
overlap. In this step, the tool will move the instances in nearby
places to overcome the overlap. To match the proper power
pins like the VDD pin of a standard cell should be on the VDD
rail and VSS on VSS rail and for that if the flipping of instance
is required tool also do the flipping. This process is called
legalization.
 PLACEMENT
4.( high fan out net synthesis :
Initially, there are some nets which have very high numbers of fanout.
We have a constraint of maximum fanout, so we need to distribute the sinks on nets
to different drivers.
The process of adding buffers and splitting the fanout is called high fanout net
synthesis (HFNS). So In this step, all high fanout nets get synthesize
 The buffering of high fan out nets to balance the load.
If you are not balance the load , transition time and delay is more
 PLACEMENT STAGES

5.Iteration (the repetition of a process):for Congestion, Timing, DRV, and Power Optimization:
 In this step tool first, do an early global route and estimate the routing overflow/congestions in the design.

 The tool tries to initially minimize the congestion in this stage.

 Next, the tool starts the RC extraction to calculate the delay for setup analysis.

 The tool tries to minimize the setup WNS(Worst –Ve Slack) and TNS(Total –Ve Sack) in this step.

 Similarly, the tool also tries to minimize the DRV and Power in this stage.

6.Timing optimization iterations:

 This is a long step in which the tool tries to minimize the WNS and TNS of each path group in various iterations .

 There are several iterations required to get a minimum WNS and TNS depending upon the effort set and initial WNS number .

 In case the result is not good after this stage,

 we can further run incremental optimization for timing. Similarly, for congestion ,
 we can run congestion repair followed by incremental optimization to get a better result. But these additional steps will increase the run time
7.Scan chain reordering
This is nothing but scan-chain reordering.
 Scan-chain reordering helps to Reduce congestion and Total wire-length
Before After
 PLACEMENT
1.Placement Can be Done as
1.Timing Driven: Tool tries to place the standard cells along timing critical path close together to reduce net RC and meet setup timing .
check: create_placement -timing

2.Congestion Driven: when path for routability, Tool tries to spread the cells where the density of cells are more for the reduction of congestion .
Check: create_placement -congestion
3.Power Driven: In a library contains multiple-threshold- voltage cells,
 The LVT cells have higher leakage current but better performance.

 The HVT cells have lower leakage current but worst performance.

 Percentage low threshold voltage optimization tries to find a balance between power and performance goals restricted the use of LVT cells.

 During low power placement, the tool tries to minimize the length of high switching nets to improve the power QOR.

 During Dynamic power-driven placement, the tool tries to improve both the timing and power of the critical nets and the power QOR
without affecting the timing QOR.
PLACEMENT BOUNDS
 It is a constraint , that controls the placement of groups of leaf cells and hierarchical cells.
 When our timing is critical during placement then we create bounds in that area where two
communicating cells are sitting far from another
 By using the bounds ,we can place the same group the cells into a bound.
 The wire length can be reduced
 It can be used for avoiding the congestion also.

Types of bounds
i)Hard bound (In this tool must place the cells in the move bound within a specified region.)
ii)Soft bound (In this tool tries to place the cells in the move bound within a specified region, however,
there is no guarantee that the cells are placed inside the bounds.)
iii)Exclusive bound:(In this tool tries to place the cells in the group bound within a floating region,
however, there is no guarantee that the cells are placed inside the bound)
 OUTPUTS OF PLACEMENT & CHECKS
Outputs:
1. Physical Layout Information
2. Cell placement location
3. Physical Layout Timing and Technology information of logical librarys
Checks:
1. Check legalization command: Check_legality and report_congestion
2. Check PG connections for all the cells.
3. Check congestion, density screens & pin density maps all these should be under control
4. Timing QOR, there should not be any high WNS violations.
5. Minimum max Tran and max cap violations.
6. Check whether all don’t touch cells & nets are preserved.
7. Check the total utilization of design after placement
CHECKS AND FIXES :
➢ CHECK_LEGALITY: this command is used to check if all the standard cells are placed correctly or
aligned to the standard cell row, and also it will check if there is any overlap in the standard cells.

FIXES: this cell overlap is due to higher utilization ,the fix is to increase the die or core area, this also
might happen if manual placement of any cell is improper ,the fix could be to do the manual
placement correctly.

➢ CELL_DENSITY: This command used to check the cell density of our design, the tool will divide the
entire design into 5*5 boxes (means 5 standard cell height and 5 standard cell width), so in each box
it will check the density of cells, or in each area or box it will check the utilization. • It is only a
concern if the high-density boxes are clumped together which looks like a red colored hotspot in
the cell density map.

FIXES: create partial blockage for that particular region, and rerun the place opt,so this is how we
can control the standard cell placement in certain regions.
➢ CHECK CONGESTION IN GUI: Check the congestion map in the design, it will show the capacity and
demand (demand of metal tracks and capacity of metal tracks)of a particular GRC (global routing
cell),if demand greater than capacity then it is overflow, if demand less than capacity then it is
under flow. It is of a concern only when all the GRCS with high overflow are next to each other (as
detours can be performed if high overflow grcs are spread)
● The congestion is mainly due to high pin density in a particular region, this can be due to
complex AOI or OAI cells sitting next to each other.
● To tell if congestion is due to high pin density, congestion map and pin density map can be
opened parallelly.
FIXES: if the congestion is due to AOI OR OAI cells sitting next to each other, the fix will be ,give cell
padding or keep out margin between AOI or OAI cells to avoid congestion issues .
➢ Another cause of congestion is insufficient macro to macro spacing, this will cause congestion.
FIXES: To avoid the congestion due to insufficient macro spacing, go back to floor plan and increase
the channel spacing as appropriate.
➢ Another reason for congestion is the lower number of routing tracks available around macro
corners.
FIXES: create partial blockage around macro corners.
➢ REPORT_CONSTRAINTS : this command can be used to check setup ,max tran ,max cap, and hold
violations
➢ PLACEMENT_UTILIZATION: This command used to check the utilization jump from floor plan to
after placement. After placement if you are seeing the higher utilizations this may be due the
addition of buffers during place_opt,or due to over buffering in the place_opt stage .
FIXES: if the higher utilization after place_opt is due to over buffering ,then its due to tighter max
tran limit,the max tran limit is too less the tool will try to over buffer to meet the transition
requirement, so ,check the max tran limit ,and change it.
➢ SETUP violation cause:
➢ It can be due to too many buffers added in the Datapath.
FIXES: create bounds to avoid logic spread to reduce the number of buffers.
➢ Another reason for over buffering can be a tight limit on max tran/max cap.
FIXES:
● So this can be fixed by giving a reasonable max tran/max cap limit.
● If the setup violations are limited then, use a group path with critical range and give more
weightage for these endpoints.
➢ Another cause can be unoptimized nets (if there is any don’t touch on the net, then it will cause
setup violations).
FIXES: remove the don’t touch on the particular net and rerun the place_opt.
➢ Another cause can be, if two hierarchy cells have many data paths which are too long, this can also
cause setup violations.
FIXES: create soft bound for the two hierarchies and rerun the place_opt.
➢ Another reason can be if a net is crossing to macros which have no space between them the net
cannot be buffered leading to bad transitions and setup violations.
FIXES: move the macros apart and create a soft blockage between them ,so that there is enough
space to add a buffer.
➢ MAXTRAN and MAXCAP : The max tran and max cap violations can be due to non bufferable
regions,high fanout,lower drive strength cells ,long nets .

FIXES:if the violations are due to long nets then add the buffer, if the violation is due to weak driver
then upsize the driver ,check if max transaction limit is there are not, the violations can be due to
non bufferable regions, if the max cap violations are due to tie cells .then change the tie cell fanout
,to reduce maxcap violations.

➢ ANALYZE_DESIGN_VIOLATIONS -ALL_VIOLATORS ,there are many options in this command like

maxtran, setup, max capacitance. By using this command with a particular option, we can find the
various reasons behind that violation, it will show all categories of violations.

➢ REPORT_QOR This command can be used to get the number of violating paths ,worst negative slack
and total negative slack, and how many paths are violating in each scenario.