COMPUTER ORGANIZATION

AND
ARCHITECTURE
(KCS 302)
Topic: UNIT 1

Jyoti Guglani
Department of Computer Science & Engineering
IMS ENGINEERING COLLEGE
Dr. A.P.J. Abdul Kalam Technical University,
Lucknow
 NUMBER SYSTEM

• Number System is used for representing the information. Human

communicate with each other in a particular language made of letters or
words. We write the information through keyboard of the computer, but
computer does not understand the words or letters. So that those words
and letters are translated into numbers. This means that computers
understand only numbers.
• Number system has different bases:-
 Decimal (10)
 Binary (2)
 Octal (8)
 Hexadecimal (16)
 NUMBER SYSTEM

 Number System are two types:-

1) Positional Number System
2) Non- Positional Number System
• In Positional Number System, position of each digit of a number has
some weight. Each count start from Zero. For example:-
5629= 5*103 +6*102 +2*101 +9*100 =5000+600+20+9 = 5629
 NUMBER SYSTEM

Similarly
5239.6518= 5*103 +2*102 +3*101 +9*100 +6*10-1+5*10-2+1*10-3+8*10-4
Each digit in a number system can be determined as Integer part and
fractional part.
• In Non-positional number system, a digit of a number does not
indicate any significance in position and weight, zero is absent in
these type of systems and these are roman numerical System.
 NUMBER SYSTEM

Different types of Number system:-

• Decimal number system:- This System has 10 base value,
digits between(0-9) and each digit represents a position or a
weight value so it is called positional weight number system.
For example :- 7739.4538= 7*103 +7*102 +3*101 +9*100 +4*10-
1
+5*10-2+3*10-3+8*10-4
 NUMBER SYSTEM

•Binary number system:- This System has 2 base value, digits are (0,1) and each
digit represents a position or a weight value so it is called positional weight
number system.
For example :- 111.111
1*22 +1*21 +1*20 +1*2-1+1*2-2+1*2-3
• Octal Number System:- This System has 8 base value, digits between (0-7) and
each digit represents a position or a weight value so it is called positional weight
number system.
For example :- 456.345
4*82 +5*81 +6*80 +3*8-1+4*8-2+5*8-3
 NUMBER SYSTEM

•Hexadecimal number system:- This System has 16 base value, digits between
(0-15) and each digit represents a position or a weight value so it is called
positional weight number system.
For example :- 879.ABC
8*162 +7*161 +9*160 +A*16-1+B*16-2+C*16-3

SYSTEM Base or Radix Digits or Symbols

Binary 2 0-1
Decimal 10 0-9
Octal 8 0-7
Hexadecimal 16 0-15
 NUMBER SYSTEM

CONVERSIONS:-
•Any Base to Decimal
•Decimal to Any Base
•Octal to Binary
•Octal to Hexadecimal
•Binary to Octal
•Binary to Hexadecimal
•Hexadecimal to Binary
•Hexadecimal to Octal
 NUMBER SYSTEM

Any Base to Decimal

•It follow just three steps:
A) Determine the base value of given Number System (that you want to convert),
and also determine the position of digits from LSB to MSB.
B) Multiply each digit with its corresponding multiplication of position value and
Base of given Number System’s Base.
C) Add the resulted value in step-B.
•For example:- (1101.11)2 ( )10 Binary  Decimal
1*23+1*22 +0*21 +1*20 +1*2-1+1*2-2 =8+4+0+1.(.5)+(.25)=(13.75)10

•
 NUMBER SYSTEM

• (475.25)8( )10 Octal  Decimal

4*82+7*81 +5*80 +2*8-1+5*8-2 =256+56+5.(.25)+(.078125)=(317.32813)10

• (7B1.2A)16( )10 Hexadecimal Decimal

7*162+B*161 +1*160 +2*16-1+A*16-2 =1792+176+1.(.125)+(.039)=(1969.164)10

• (3100.12)4( )10 Any Base Decimal

3*43+1*42+0*41 +0*40 +1*4-1+2*4-2=48+16+0+0.(.25)+(.125)=(64.375)10
 NUMBER SYSTEM

Decimal to Any Base

• (15)10  ( )2 Decimal  Binary

2 15 1 LSB
2 7 1
2 3 1
2 1 1 MSB
 NUMBER SYSTEM

Decimal to Any Base

• (.8125)10  ( )2 Decimal  Binary
.8125 * 2=1.625 1
.625 * 2 =1.25 1
.25 * 2 = 0.50 0
.50 * 2 = 1.0 1 (when 0 comes after decimal or term repeated so stop the
process.(.1101)2
 NUMBER SYSTEM

• (214.640625)10  ( )8 Decimal  Octal

8 214 6 LSB
8 26 2
8 3 3
MSB
• (.640625)10  ( )8 =
.640625 * 8=5.125 5
.125 * 8=1.0 1 =( 326.51)8
 NUMBER SYSTEM

• (54)10  ( ) 4

Octal to Binary
• (634)8 ( )2
823 ,we can use 3 digit for conversion as binary from decimal.
6 110 , 3011 , 4100 =(110 011 100)2
• (546)8 ( )2
 NUMBER SYSTEM

Hexadecimal to Binary
• (3FD)16 ( )2
1624 ,we can use 4 digit for conversion as binary from decimal.
3 0011 , F1111 , D1101 =(0011 1111 1101)2
• (28F)16 ( )2
 NUMBER SYSTEM

Binary to Octal
• (100010011011)2 ( )8
823 ,we can use 3 digit for conversion as decimal from binary & start from LSB
to MSB.
01010011011= 001 010 011 011 =(1233)8

1 2 3 3
• (0011111100)2 ( )8
 NUMBER SYSTEM

Binary to Hexadecimal
• (100010011011)2 ( )16
1624 ,we can use 4 digit for conversion as decimal from binary & start from LSB
to MSB.
100010011011= 1000 1001 1011 =(89B)16

8 9 B
• (10011111100)2 ( )16
 NUMBER SYSTEM

Octal to Hexadecimal
• (615)8 ( )16
1. First convert in to binary
2. After converting in binary, convert it in to Hexadecimal.
(615)8 ( )2  ( )16 =(615)8 (110 001 101)2
(110 001 101)2 = (0001 1000 1101)

1 8 D
• (567)8 ( )16
 NUMBER SYSTEM

Hexadecimal to Octal
• (25B)16 ( )8
1. First convert in to binary
2. After converting in binary, convert it in to Octal.
(615)16 ( )2  ( )8 =(615)16(0110 0001 0101)2
(0110 0001 0101)2 = (011 000 010 101)=(3025)8

3 0 2 5
• (567B)16 ( )8
 Assignment
Convert the Following:-
Q1:- (1111.10)2 ( )10
Q2:- (564.66)8 ( )10
Q3:- (54.50)10 ( )2
Q4:- (67AB.AA)16( )8
Q5:- (321.30)5 ( )10
Q6:- (675)10( )4
 Arithmetic Binary System

The basics of arithmetic binary system are binary addition,

Subtraction, Multiplication and Division.
Binary Addition:- Rules for binary addition

Digital Logic Design

 Arithmetic Binary System

 Example of binary addition :-

111
10110.10
01011.00
carry bit 100001.10
1110.10 + 001.00=
 Arithmetic Binary System

Binary Subtraction:- Rules for binary Subtraction

Case A - B SUBTRACT BORROW

1 0 - 0 0 0
2 0 - 1 1 1
3 1 - 0 1 0
4 1 - 1 0 0
 Arithmetic Binary System

Binary Multiplication:- Binary multiplication is same as decimal

multiplication. It involves only 0s and 1s . Rules of binary multiplication:-
 Arithmetic Binary System

Binary Division:- Binary Division is same as Division. It involves only 0s and 1s .

Rules of binary Division :-
 Arithmetic Binary System

The basics of arithmetic binary system are binary addition,

Subtraction, Multiplication and Division.
Binary Addition:- Rules for binary addition
 Arithmetic Binary System

 Example of binary addition :-

111
10110.10
01011.00
carry bit 100001.10
1110.10 + 001.00=
 Arithmetic Binary System

Binary Subtraction:- Rules for binary Subtraction

Case A - B SUBTRACT BORROW

1 0 - 0 0 0
2 0 - 1 1 1
3 1 - 0 1 0
4 1 - 1 0 0
 Arithmetic Binary System
Compliments of Binary Number: (r is radix/base)
r’s Compliment - 2’s compliment
(r-1)’s Compliment - 1’s compliment

To find 1’s compliment of binary number convert all 1’s into 0’s. And all 0’s into
1’s.
To find the 2’s compliment of binary number find find the 1’s complement and
add 1 to right most bit.
or start from right most bit write number as it is till first 1 arrives and than
take 1’s compliment of remaining bits.
 Subtraction using 1’s compliment method
• Write first number as it is. Take 1’s complement of second number.
Add the numbers to get resultant.
• If carry is genetated, add the carry to right most bit and get the final
result.
• If NO carry is generated , than take 1’s compliment of resultant and
put negative sign in front of it to get the final result.
 Subtraction using 2’s compliment method
• Write first number as it is. Take 2’s complement of second number.
Add the numbers to get resultant.
• If carry is genetated, discard the carry to get the final result.
• If NO carry is generated , than take 2’s compliment of resultant and
put negative sign in front of it to get the final result.
 Examples
Q.1: Perform the following substation using 1’s compliment method:
1100 – 1010
Sol.: 1100 1100
- 1010 0101
1 0001
Since carry is generated add carry to right most bit of resultant
0001
+ 1
Answer: 0010
 Examples
Q.2: Perform the following substation using 1’s compliment method:
1010 – 1100
Sol.: 1010 1010
- 1100 0011
1101
Since NO carry is generated take 1’s compliment of resultant with
negative sign
Answer is - 0010
 Examples
Q.3: Perform the following substation using 2’s compliment method:
1100 – 1010
Sol.: 1100 1100
- 1010 0110
10010
Since carry is generated discard the carry to get the result
Answer is 0010
 Examples
Q.4: Perform the following substation using 2’s compliment method:
1010 – 1100
Sol.: 1010 1010
- 1100 0100
1110
Since NO carry is generated take 2’s compliment of resultant with
negative sign
Answer is - 0010
 Arithmetic Binary System

Sign Magnitude:- In Signed numbers 1 bit use for sign bit(MSB) and other bits
represent magnitude. Sign bit further divided in two forms:-
1. Positive sign number :- it is represented by 0
2. Negative sign Number:- it is represented by 1
For Example:- +(8) = 0 1000 Magnitude -(8)= 1 1000 Magnitude
Sign Bit Sign Bit
 Arithmetic Binary System

Ques:- Represent (+48) and (-13) in 8 bit Signed magnitude representation.

+(48)= 0 0110000 Magnitude -(13)= 1 0001101 Magnitude

Sign Bit Sign Bit

 Arithmetic Binary System

Ques:- Represent (+48) and (-13) in 8 bit Signed 1’s compliment representation.
a) +(48)= 0 0110000 similar as Signed Magnitude Representation.

b) -(13) :- First write (+13)=00001101,then takes 1’s compliment of that

number. So the number is 11110010.
 BUS
 A bus is a communication pathway connecting two or more devices.
A key characteristic of a bus is that it is a shared transmission
medium.

a b c
Multiple devices connect to the bus, and a signal transmitted by any
one device is available for reception by all other devices attached to
the bus. so that create garble(destroyed),so for that solution we use
arbitration.
A bus is a subsystem that is used to connect computer components
and transfer data between them. For example, an internal bus
connects computer internals to the motherboard.
A bus may be parallel or serial. Parallel buses transmit data across
multiple wires. Serial buses transmit data in bit-serial format.
Data is transmitted from one part of a computer to another,
connecting all major internal components to the CPU and memory,
by the means of Buses.
 Types of Buses
System bus:- a bus consists of multiple communication pathways, or lines. Each line is
capable of transmitting signals representing binary 1 and binary 0. An 8-bit unit of data can be
transmitted over eight bus lines. A bus that connects major computer components (processor,
memory, I/O) is called a system bus
•Data Bus: It carries data among the memory unit, the I/O devices, and the processor. the
number of lines in data bus is known as width of data bus for ex :- 16,32,64 that means 16 bits
data transfer at a time. each line carries one bit at a time parallel.
• Address Bus: It carries the address of data (not the actual data) between memory and
processor. The address lines are used to designate the source or destination of the data on
the data bus.
For example, on an 8-bit address bus, address 01111111 and below might reference
locations in a memory module (module 0) with 128 words of memory,
For example:- 23 = 8 i.e. 3 address line is required to select 8 location,

2x = n
In general where x number of address lines (address bit) and n is number of location
 Types of Buses
• Control Bus: It carries control commands from
the CPU (and status signals from other devices)
in order to control and coordinate all the
activities within the computer.
BUS INTERCONNECTION STRUCTURE

The operation of the bus is as follows. If one module wishes to send data to
another, it must do two things:
(1) obtain the use of the bus, and (2) transfer data via the bus.
If one module wishes to request data from another module, it must (1) obtain the
use of the bus, and (2) transfer a request to the other module over the
appropriate control and address lines. It must then wait for that second module
to send the data.
 Bus & Memory Transfer

• A bus system with K registers of n bits. Each to

produce n line common bus system, the number
of MUX needed to construct the bus is n. The
size of each MUX must be K * 1.
• Question:-
Design a common bus system by using multiplexer if
we have 4 registers and each register has 4 bits. Also find
out :-
a) How many MUX required?
b) Find out the size of MUX.
The following block diagram shows a common Bus system for 4(K)
registers. It is constructed with the help of (K*1) 4 * 1 Multiplexers
each having n=4 inputs (0 through 3) and 2 selection inputs (S1 and
S2).
We have used labels to make it more convenient for you to
understand the input-output configuration of a Bus system for four
registers. For instance, output 1 of register A is connected to input 0
of MUX1.
The two selection lines S1 and S2 are connected to the selection inputs
of all four multiplexers. The selection lines choose the four bits of one
register and transfer them into the four-line common bus.
When both of the select lines are at low logic, i.e. S1S0 = 00, the 0
data inputs of all four multiplexers are selected and applied to the
outputs that forms the bus. This, in turn, causes the bus lines to
receive the content of register A since the outputs of this register are
connected to the 0 data inputs of the multiplexers.
Similarly, when S1S0 = 01, register B is selected, and the bus lines
will receive the content provided by register B.
The following function table shows the register that is selected by the
bus for each of the four possible binary values of the Selection lines.
 COMMON BUS SYSTEM BY USING
DECODER
• A bus system can also be constructed using tri-state gates instead of
multiplexers.
• The Tri state gates can be considered as a digital circuit that has
three state, two of which are signals equivalent to logic 1 and 0 as
input. However, the third state exhibits as a control logic. That is
defined open or closed circuit.
•If it is open then the output is high Impedance and if it is closed then
output is same as input.
The graphical
:
symbol of a three-state buffer gate can be represented
as:

Control Input Output

0 0 Z
0 1 Z
Control(C) 1 0 0
1 1 1
 Decoder

 A 2x4 Decoder is like:

Digital Logic Design

•The outputs generated by the four buffers are connected to form a
single bus line.
•Only one buffer can be in active state at a given point of time.
•The control inputs to the buffers determine which of the four normal
inputs will communicate with the bus line.
•A 2 * 4 decoder ensures that no more than one control input is
active at any given point of time.
Memory Transfer
Most of the standard notations used for specifying operations on memory transfer are
stated below.
•The transfer of information from a memory unit to the user end is called
a Read operation.
•The transfer of new information to be stored in the memory is called a Write operation.
•A memory word is designated by the letter M.
•We must specify the address of memory word while writing the memory transfer
operations.

•.
 VON NEUMANN ARCHITECHURE
• Von Neumann architecture was first published by John von
Neumann in 1945. Von Neumann architecture is based on the
stored-program computer concept, where instruction data and
program data are stored in the same memory.
VON NEUMANN ARCHITECHURE

MAIN MEMORY

Program
Data
or
A=10;
instructio
B=5
n
C=A+B
 COMPUTER ORGANISATION AND ARCHITECTURE
• The components from which computers are built,
i.e., computer organization.
• In contrast, computer architecture is the science of
integrating those components to achieve a level of
functionality and performance.
• It is as if computer organization examines the
lumber, bricks, nails, and other building material
• While computer architecture looks at the design of
the house.
 Computer organization
• It is concerned with the way hardware
components operate and the way they are
connected to form a computer system.
• The various components are assumed to be in
place and the task is to investigate the
organizational structure to verify that the
computer parts operated as intended.
• Computer Organization refers to the level of
abstraction above the digital logic level, but below
the operating system level.
 Computer Design
• Computer design is concerned with the hardware
design of the computer.

Once the computer specifications are formulated, it is
the task of the designer to develop hardware for the
system.

Computer design is concerned with the determination
of what hardware should be used and how the parts
should be connected.

This aspect of computer hardware is sometimes
referred to as computer implementation.
 Computer Architecture

Computer Architecture is a functional description of

requirements and design implementation for the various
parts of computer. It is concerned with the structure and
behavior of the computer as seen by the user. It includes the
information formats, the instruction set and techniques for
addressing memory. The architectural design of a computer
system is concerned with the specifications of the various
functional modules, such as processors and memories, and
structuring them together into a computer system.
 Difference between Computer Organization and
Architecture
Computer Organization Computer Architecture

Organization describes how it does it. Architecture describes what the computer does.

Computer Organization deals with structural relationship. Computer Architecture deals with functional behavior of
computer system.

Where, Organization indicates its hardware. Architecture indicates its performance.

Computer Organization is frequently called as micro Computer Architecture is also called as instruction set
architecture. architecture.

Computer Organization comprises physical units such as Computer Architecture consists logical functions such as
adders, decoders etc. instruction sets, registers, data types and addressing
modes

Computer Organization handles the segments of the Architecture coordinates between the hardware and
network in a system. software of the system.
FUNCTIONAL UNITS OF COMPUTER
 FUNCTIONAL UNITS OF
COMPUTER
• Input Unit

• Output Unit

• ALU

• Control Unit

• Memory Unit
Input Unit: Computer accepts encoded information
through input unit. The standard input device is a keyboard.
Whenever a key is pressed, keyboard controller sends the
code to CPU/Memory. Converts the external world data to
a binary format, which can be understood by CPU.

Examples are Mouse, Joystick, Tracker ball, Light pen,

Digitizer, Scanner etc.

Output unit: Converts the binary format data to a format

that a common man can understand Computer after
computation returns the computed results, error messages,
etc. via output unit.

Examples are Monitor, Printer, LCD, LED etc

Memory unit stores the program instructions (Code), data and results
of computations etc.
 Memory unit is classified as:
• Primary /Main Memory • Secondary /Auxiliary Memory.
 Primary memory is a semiconductor memory that provides access at
high speed. Run time program instructions and operands are stored
in the main memory. Main memory is classified again as ROM and
RAM. ROM holds system programs and firmware routines such as
BIOS, POST, I/O Drivers that are essential to manage the hardware of
a computer. RAM is termed as Read/Write memory or user memory
that holds run time program instruction and data. While primary
storage is essential, it is volatile in nature and expensive.
Secondary memory are non volatile in nature. Secondary
memory refers to storage devices, such as hard drives and solid state
drives. It may also refer to removable storage media, such as USB
flash drives, CDs, and DVDs. secondary memory is not accessed
directly by the CPU.
•ALU: -An arithmetic-logic unit (ALU) is the part of a computer
processor (CPU) that carries out arithmetic and logic operations
on the operands in computer instruction words. ALU consist of
necessary logic circuits like adder, comparator etc, to perform
operations addition, multiplication, AND,OR,XOR,NOR,NAND.

•Control Unit:- Control unit co-ordinates activities of all units

by issuing control signals. Control signals issued by control unit
govern the data transfers and then appropriate operations take
place. Control unit interprets or decides the operation/action to be
performed. That also divide in to two type of signals:-
•Timing signal:- which instruction is being executed first that is
dependent on it.
•Control signal:- control all the registers ,that how we can use all
these.
 Bus Arbitration
• Bus Arbitration refers to the process by which the current bus master
accesses and then leaves the control of the bus and passes it to the
another bus requesting processor unit. The controller that has access
to a bus at an instance is known as Bus master.
• The selection of the bus master must take into account the needs of
various devices by establishing a priority system for gaining access to
the bus. The Bus Arbiter decides who would become current bus
master.
• There are two approaches to bus arbitration:
1. Centralized bus arbitration – A single bus arbiter performs
the required arbitration.
2. Distributed bus arbitration – All devices participate in the
selection of the next bus master.
 Methods of Bus Arbitration
There are three bus arbitration methods:
• Daisy Chaining method –
It is a centralized bus arbitration method. During any bus cycle, the
bus master may be any device – the processor or any DMA controller
unit, connected to the bus.
 Methods of Bus Arbitration
Daisy Chaining method:

Advantages –
•Simplicity and Scalability.
•The user can add more devices anywhere along the chain, up to a certain
maximum value.
Disadvantages –
•The value of priority assigned to a device is depends on the position of master
bus.
•Propagation delay is arises in this method.
•If one device fails then entire system will stop working.
 Methods of Bus Arbitration
• Polling or Rotating Priority method –
In this method, the devices are assigned unique priorities and complete to access the bus, but the
priorities are dynamically changed to give every device an opportunity to access the bus.
 Methods of Bus Arbitration
Polling or Rotating Priority method

Advantages –
•This method does not favor any particular device and processor.
•The method is also quite simple.
•If one device fails then entire system will not stop working.

Disadvantages –
•Adding bus masters is difficult as increases the number of address lines
of the circuit.
 Methods of Bus Arbitration
• Fixed priority or Independent Request method –
In this method, the bus control passes from one device to another only through the centralized bus arbiter.
 Methods of Bus Arbitration

Fixed priority or Independent Request method:

Advantages –
•This method generates fast response.

Disadvantages –
•Hardware cost is high as large no. of control lines are required.
Interconnection between Processor and Memory
Registers
Registers are fast stand-alone storage locations that hold data
temporarily. Multiple registers are needed to facilitate the
operation of the CPU. Some of these registers are

 Two registers-MAR (Memory Address Register) and

MDR (Memory Data Register) : To handle the data
transfer between main memory and processor. MAR-
Holds addresses, MDR-Holds data
 Instruction register (IR) : Hold the Instructions that is
currently being executed
 Program counter: Points to the next instructions that is
to be fetched from memory
•(PC) (MAR)( the contents
of PC transferred to MAR)

•(MAR) (Address bus) Select a

particular memory location

•Issues READ control signals

•Reads instruction present in memory

and loaded into (Data Bus)MDR

•Will be placed in IR (Contents

transferred from MDR to IR)
•Instruction present in IR will be decoded by
which processor understand what operation it
has to perform

•Increments the contents of PC by 1, so that it

points to the next instruction address

•If data required for operation is available in

register, it performs the operation

•If data is present in memory following

sequence is performed
•Address of the data MAR

•MAR Address bus select memory

location where is issued RD signal

•Reads data via data bus MDR

•From MDR data can be directly routed to ALU

or it can be placed in register and then
operation can be performed

•Results of the operation can be directed

towards output device, memory or register

•Instruction Executed.
 Types of Addressing Modes
The different ways in which the location of the operand is
specified in an instruction are referred to as addressing
modes

• Immediate Addressing
• Direct Addressing
• Indirect Addressing
• Register Addressing
• Register Indirect Addressing
• Relative Addressing
• Indexed Addressing
 Immediate Addressing
• Operand is given explicitly in the instruction
• Operand = Value
• e.g. ADD 5
– Add 5 to contents of accumulator
– 5 is operand
• No memory reference to fetch data
• Fast
• Limited range

Instruction
opcode
operand
 Direct Addressing
• Address field contains address of operand
• Effective address (EA) = address field (A)
• e.g. ADD A
– Add contents of cell A to accumulator
– Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out effective address
• Limited address space
 Direct Addressing Diagram
Instruction
Opcode Address A
Memory

Operand
 Indirect Addressing (1)
• Memory cell pointed to by address field contains the address
of (pointer to) the operand
• EA = [A]
– Look in A, find address (A) and look there for operand
• e.g. ADD (A)
– Add contents of cell pointed to by contents of A to accumulator
 Indirect Addressing (2)
• Large address space
• 2n where n = word length
• May be nested, multilevel, cascaded
– e.g. EA = (((A)))
• Draw the diagram yourself
• Multiple memory accesses to find operand
• Hence slower
 Indirect Addressing Diagram
Instruction
Opcode Address A
Memory

Pointer to operand

Operand
 Register Addressing (1)
• Operand is held in register named in address field
• EA = R
• Limited number of registers
• Very small address field needed
– Shorter instructions
– Faster instruction fetch
 Register Addressing (2)
• No memory access

• Very fast execution

• Very limited address space

• Multiple registers helps performance

– Requires good assembly programming or compiler writing
 Register Addressing Diagram
Instruction
Opcode Register Address R
Registers

Operand
 Register Indirect Addressing
• C.f. indirect addressing
• EA = [R]
• Operand is in memory cell pointed to by contents of register R
• Large address space (2n)
• One fewer memory access than indirect addressing
Register Indirect Addressing Diagram
Instruction
Opcode Register Address R
Memory

Registers

Pointer to Operand Operand

 Indexed Addressing
• EA = X + [R]
• Address field hold two values
– X = constant value (offset)
– R = register that holds address of memory locations
– or vice versa
 (Offset given as constant or in the index register)
Add 20(R1),R2 or Add 1000(R1),R2
Indexed Addressing Diagram
Instruction
Opcode Register R Constant Value
Memory

Registers

Pointer to Operand + Operand

 Relative Addressing
• A version of displacement addressing
• R = Program counter, PC
• EA = X + (PC)
• i.e. get operand from X bytes away from current location
pointed to by PC
• c.f locality of reference & cache usage
 Auto increment mode
• The effective address of the operand is the
contents of a register specified in the instruction.
• After accessing the operand, the contents of this
register are automatically incremented to point
to the next item in the list
• EA=[Ri]; Increment Ri ---- (Ri)+
Eg: Add (R2)+,R0
 Auto decrement mode
• The contents of a register specified in the instruction are first
automatically decremented and are then used as the effective
address of the operand

• Decrement Ri; EA= [Ri] ----- -(Ri)

 Addressing Architecture
• Memory-to-Memory architecture
– All of the access of addressing -> Memory
– Have only control registers such PC
– Too many memory accesses
• Register-to-Register architecture
– Allow only one memory address
• “load”, “store” instructions
• Register-to-Memory architecture
– Program lengths and # of memory accesses tend to be intermediate
between the above two architectures
• Single accumulator architecture
– Have no register profile
– Too many memory accesses
• Stack architecture
– Data manipulation instructions use no address.
– Too many memory (stack) accesses
– Useful for rapid interpretation of high-level lang. programs in which the
intermediate code representation uses stack operations.
 Addressing Modes
• Implied mode
– The operand is specified implicitly in the definition of the opcode.
• Immediate mode
– The actual operand is specified in the instruction itself.
Addressing Modes (Summary)

Base register LDA #ADRS(R1) ACC <- M[R1+ADRS]

 Instruction Set Architecture
• RISC (Reduced Instruction Set Computer) Architectures
– Memory accesses are restricted to load and store instruction, and
data manipulation instructions are register to register.
– Addressing modes are limited in number.
– Instruction formats are all of the same length.
– Instructions perform elementary operations

• CISC (Complex Instruction Set Computer) Architectures

– Memory access is directly available to most types of instruction.
– Addressing mode are substantial in number.
– Instruction formats are of different lengths.
– Instructions perform both elementary and complex operations.
 Instruction Set Architecture
• RISC (Reduced Instruction Set Computer) Architectures
– Large register file
– Control unit: simple and hardwired
– pipelining

• CISC (Complex Instruction Set Computer) Architectures

– Register file: smaller than in a RISC
– Control unit: often micro-programmed
– Current trend
• CISC operation  a sequence of RISC-like operations
Characteristics of RISC Vs CISC processors
No RISC CISC
1 Simple instructions taking one Complex instructions taking
cycle multiple cycles
2 Instructions are executed by Instructions are executed by
hardwired control unit microprogramed control unit
3 Few instructions Many instructions

4 Fixed format instructions Variable format instructions

5 Few addressing mode, and most Many addressing modes

instructions have register to
register addressing mode
6 Multiple register set Single register set

7 Highly pipelined Not pipelined or less pipelined

 Register Transfer language
• A digital computer system exhibits an
interconnection of digital modules such as registers,
decoders, arithmetic elements, and Control logic.
• These digital modules are interconnected with
some common data and control paths to form a
complete digital system.
• Moreover, digital modules are best defined by the
registers and the operations that are performed on
the data stored in them.
• The operations performed on the data stored in
registers are called Micro-operations.
 MICROINSTRUCTIONS &
OPERATIONS
• R1: A+B
• R1 M[A] + M[B] MICRO OPERATION
• R1 M[A] + M[B] ,R2  R1 MICRO INSTRUCTION

• A micro-operation is an elementary operation

performed on the information stored in one or more
registers, the result of the operation may replace the
previous binary information or may be transfer to
another registers.
• Examples of micro operations are:-
shift ,count, clear and load
 Register Transfer language
The Register Transfer Language is the symbolic representation of
notations used to specify the sequence of micro-operations and
transfer the result of the operation to the same or another
register.
The internal hardware organization of a digital system is best
defined by specifying:
• The set of registers and the flow of data between them.
• The sequence of micro-operations performed on the data which
are stored in the registers.
• The control paths that initiates the sequence of micro-operation
• Computer registers are designated by capital letters:-
• MAR ,MBR IR
• In a computer system, data transfer takes place between
processor registers and memory and between processor
registers and input-output systems. These data transfer
can be represented by standard notations given below:
• Notations R0, R1, R2..., and so on represent processor
registers.
• The addresses of memory locations are represented by
names such as LOC, PLACE, MEM, etc.
• Input-output registers are represented by names such as
DATA IN, DATA OUT and so on.
• The content of register or memory location is denoted by
placing square brackets around the name of the register or
memory location.
 Types of instruction
• Data transfer instruction
• Data manipulation instruction
• Program control instruction
 Data transfer instruction
• The data transfer instructions are used to transfer data from
one location to another. This transfer of data can be either
from register to register, register to memory or memory to
register. It is important to note here that the memory to
memory transfer of data directly is not possible.
• Following are some instructions that are used for data
transfer purpose:
• MOV LOAD
• PUSH XCHG
• POP IN OUT
• STORE
 Data manipulation instruction
Data manipulation have arithmetic operations, logical
operations and shift operations.
Arithmetic operations :-
1.ADD 5. INC
2.SUB 6. DEC
3.MUL 7. ADD With Carry
4.DIV 8. Subtract with borrow 9. Negate
Logical Operations:-
1.Compliment (COM) 4. Ex-OR 7. Set carry
2.CLEAR(CLR) 5. Clear Carry 8. Compliment carry
3.Logical AND 6. Logical OR 9.Enable
Interrupt/Disable
 Data manipulation instruction

Shift operations:-
1.Logical Shift left
2.Logical shift right
3.Arithmetic shift left
4.Arithmetic shift right
5.Rotate left
6.Rotate right
7.Rotate left with carry
8.Rotate right with carry
 Program Control Instructions
When CPU process the data from consecutive
memory locations so each time one instruction is
fetched from memory and the program counter is
incremented.
It has two types of instructions:-
1)Unconditional
2)Conditional
Unconditional:- An unconditional branch instruction
means control proceeds the next instruction in
sequence.
Conditional:- A conditional branch instruction means
control proceeds the next instruction when the
condition met .
 Program Control Instructions
• JUMP
• SKIP
• BRANCH
• CALL
• RETURN
• COMPARE
General Purpose Register Organization
General Purpose Register Organization
Generally CPU has seven general registers. Register
organization show how registers are selected and how
data flow between register and ALU. A decoder is used
to select a particular register. The output of each
register is connected to the multiplexers to form the
two buses A and B. The selection lines in each
multiplexer select the input data for the particular bus.
The A and B buses form the two inputs of an ALU. The
operation select lines decide the micro operation to be
performed by ALU. The result of the micro operation is
available at the output bus. The output bus connected
to the inputs of all registers, thus by selecting a
destination register it is possible to store the result in it.
 • STACK ORGANIZATION

Stack is a storage structure that stores information in such a way

that the last item stored is the first item retrieved. It is based on
the principle of LIFO (Last-in-first-out). The stack in digital
computers is a group of memory locations with a register that
holds the address of top of element. This register that holds the
address of top of element of the stack is called Stack Pointer.

• Stack Operations

The two operations of a stack are:

• Push: Inserts an item on top of stack.
• Pop: Deletes an item from top of stack.
In digital computers, stack can be implemented in two ways:
1.Register Stack
2.Memory Stack

Register Stack

A stack can be organized as a collection of finite number of registers that are used to store
temporary information during the execution of a program.
The stack pointer (SP) is a register that holds the address of top of element of the stack.

Memory Stack

A stack can be implemented in a random access memory (RAM) attached to a CPU.

The implementation of a stack in the CPU is done by assigning a portion of memory to
a stack operation and using a processor register as a stack pointer.
The starting memory location of the stack is specified by the processor register
as stack pointer.
THANK YOU
STUDENTS

Be Safe and Stay at home