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Serial Adder
Serial Adder
x ck reset
even
odd
X=0 or reset=1
Synchronous state machine (clock input ck) States: even or odd number ones appeared at
Port x since a reset (reset=1) z <= 0 when even and 1 when odd
Hardware Description
entity parity_checker is port(x, reset, ck: in std_logic; z: out std_logic); end parity_checker; Architecture behav of parity_checker is Type state is (even, odd); Signal n_s : state; Begin Process(ck) Begin If ck=1 then Case n_s is When even => Z <= 0; If x=1 and reset=0 then n_s <= odd end if;
a b
ck reset
No_carry
carry
a+b<9 or reset=1
Operand digits at Port a and b Apply the operands starting from the least
significant digits after a reset State machine with two states
Hardware Description
entity decimal_serial_adder is port( a, b: in integer; reset, ck: in std_logic; z: out integer); end decimal_serial_adder; Architecture behav of decimal_serial_adder is Type state is (no_carry, carry); Signal n_s : state; Begin Process(ck) Begin If ck=1 then Case n_s is When no_carry => Z <= a+b mod 10; If a+b<10 or reset=1 n_s <= no_carry; elsif a+b>9 and reset=0 then n_s <= carry; else null;
a b
ck reset
No_carry
carry
a+b<r-1 or reset=1