Digital Logic

Lecture 9

Combinational Logic: Binary

Adder-Subtractor and Magnitude
Comparator

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Computer Engineering Department
Outline
 Introduction.
 Binary adders.
 Binary subtractors.
 Magnitude comparators.

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Introduction
 Till now we have introduced logic gates concepts and
combinational circuits design procedure.
 Logic gates are the basic components in digital
computer systems.
 The basic operations performed by computers are
arithmetic operations (+, -, *, /).
 Chapter 1 shows how addition and subtraction are
performed in the binary system (i.e. how they are
performed by digital computers).
 In this lecture we will design adders and subtractors
from the basic logic gates introduced in Chapter 2 in
addition to binary magnitude comparators.
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Binary Adders I
 Binary addition consists of adding two bits
with a sum and carry out result.
 To add n-bit binary numbers do the following:
 Add corresponding bits that have the same
significance locations starting from the LSBs.
 The carry out from the lower order significant bits
will added to the bits in the next higher order
significant location.
 Check if there is overflow or not.

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Binary Adders II
 Two types of binary adders:
 Half adders: add two bits only and have a result of 1-bit sum
and 1-bit carry out.
 Full adders: add three bits (the two bits to be added in
addition to carry in (Cin) bit) and have a result of 1-bit sum
and 1-bit carry out.
 Full adder is simply a two cascaded half adders.
 To add n-bit numbers full adders are used where the
Cin of bits in location i is the Cout comes from addition
of the bits in location i-1.
 Adders are combinational circuits where we will study
the design of both full and half adders.
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Half Adder Design
 Half adders takes two inputs x and y
and has two outputs: sum (S) and carry
out (C or Cout).
 Truth table:
x y S C Without using K-map it is
0 0 0 0 apparent that S is the
0 1 1 0 output on an XOR gate
1 0 1 0 and C is the output of an
1 1 0 1 AND gate.
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Half Adder Circuit

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 Full Adder Design I
 Has three inputs: the two
bits to be added (x and y) x y z S C
and the carry out coming 0 0 0 0 0
from the lower significant 0 0 1 1 0
bits (called Cin and simply 0 1 0 1 0
we will denote it here as 0 1 1 0 1
z). 1 0 0 1 0
 Has two outputs: S and Cout 1 0 1 0 1
(or C). 1 1 0 0 1
 Truth table: 1 1 1 1 1

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Full Adder Design II
 Simplify the expression of both S and C using K-map:

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Full Adder Circuit I
 Two options exist:
 Either as SOP form for both S and C.
 Or using two half adders and an OR gate.
 For the second option:
 The first half adder adds x and y. then the result is added to
z using the second half adder. Since S is obtained using an
XOR gate in a half adder, for a full adder we have the
following:
S  x y z
 For C: the carry from the first half adder = xy, whereas the
carry from the second half adder = z(xy’+x’y), combining
the two caries using OR gate you obtain:
C = xy + xy’z + x’yz
Simplify using K-map you get the same C obtained in the
previous slide.
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Full Adder Circuit -- SOP

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Full Adder Circuit – Two Half
Adders

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Binary Adder Design
 To add two n-bits numbers simply use n full adders
in cascade where the Cout of a two bits is connected
to Cin of the higher order significant bits.
 It is called n-bit binary ripple carry adder (why
ripple?).
 Also it is called n-bit parallel adder since all the
inputs (all bits of the two numbers to be added and
Cin for the LS adder) are available at the same time
for processing.
 The LSB has a subscript of 0 and the MSB has a
subscript of n-1.
 Cin for LSB adder = 0.
 An example: 4-bit binary adder.
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4-bit Binary Adder Block
Diagram

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 Propagation Delay
 Logic gates needs time for processing the input to
produce the output.
 This processing time is called propagation delay.
 For a logic circuit the total propagation delay = d 1 + d2
+ ... + dn, where dn is the delay for level n in the
circuit.
 Delay of level n in a circuit = the longest propagation
delay of all gates found in that level.
 For n-bit adder, propagation delay = n*delay of full
adder.

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Carry Propagation I
 For n-bit binary adder, even though all inputs are
available in parallel at the same time, each adder
must wait for the Cin coming from the lower order
adder to start operation.
 FA0 needs 0 time to start.
 FA1 needs (1*propagation delay) to start.
 FA2 needs (2* propagation delay) to start.
 And so on.
 So, out binary adder is not 100% parallel since the
full adders cannot work with each other at the same
time.
 This concept is called carry propagation in binary
adders.
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Carry Propagation II
 The concept of carry propagation limits the speed of
the adder.
 A solution for such problem is to make the carry
ready for all adders from the beginning.
 This is done by generating the carry based on the
inputs using special hardware.
 An adder with a carry generator is called carry look
ahead adder.
 Such adder is 100% parallel since it becomes a 1
level circuit.
 The propagation delay ≈ 1-level delay.
 However, such speed is achieved on the expense of
more complex hardware and so more cost.
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 Binary Subtractor
 Remember that to subtract two signed or unsigned
numbers you take the complement of the –ve numbers
and add them.
 The most commonly used complement system is the 2’s
complement.
 2’s complement = 1’s complement + 1
 Remember that 1 XOR x = x’, so the to get the 1’s
complement just XOR the number with 1.
 To reduce the cost of the needed hardware computers
perform addition and subtraction using the same circuit
as shown in the next slide.
 Also, remember that both signed and unsigned numbers
are added and subtracted using the same logic. So, the
same circuit can be used for the arithmetic of both
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4-bit Binary Adder-Subtractor
Block Diagram

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Notes
 The logic circuit shown in the previous slide
do the following two operations only (for both
signed and unsigned numbers):
 A+B
 A–B
 Why not –A – B?
 Do we need an extra adder to perform –A –
B?

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Magnitude Comparator
 Is a combinational circuit that determines the relative
magnitude of two numbers.
 Specifically, for two numbers A and B, the magnitude
comparator determines whether:
 A=B
 A>B
 A<B
 So, the comparator IC has three outputs for the
three above relations. It produces a high (1) on the
suitable output. For example: A = 1111 and B =
1111 then the pin the defines A = B will have a value
of 1 and the other two pins (A > B and A < B) will
have a value of 0.

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2-bit Magnitude comparator

(X > Y) = X1 X0 Y0’ + X1 Y1’ + X0 Y1’ Y0’

(X < Y) = ???
(X = Y) = ??? The Hashemite University 22
Magnitude Comparator Design I
 The usual design approach in digital logic is
to list all possible inputs combinations and
determines the output for each combination
via a truth table.
 If we use this method with comparator then:
 To compare two n-bit numbers we need 22n
entries in this truth table.
 However, we will follow a simple and efficient
design approach similar to how humans are
thinking.
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 Magnitude Comparator Design II
 A=B
 To compare two n-bits numbers you compare
the corresponding bits in them.
 Express A as AnAn-1 ... A3A2A1A0 and Express B
as BnBn-1 ... B3B2B1B0.
 To have A = B you must have An = Bn, An-1 =
Bn-1 ... A1 = B1, and A0 = B0
 Remember that an XNOR gate determines
whether two bitsTheare equal or not.
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Magnitude Comparator Design III
 For two n-bit numbers you need n XNOR gates.
 However, you need one bit output if = 1 then A =
B and 0 otherwise.
 So, combine the output of all XNOR gates via AND
gate if the output of this AND gate = 1 then A = B
and 0 otherwise.
 For a 4-bit magnitude comparator lets the output
of the XNOR gates designated as x3, x2, x1, x0
where x3 = A3 XNOR B3 and so on, then:
(A = B) = x3x2x1x0
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Magnitude Comparator Design IV
 A > B and A < B
 Start from the MSB of both A and B if these two bits are
equal then compare the next pair of bits located in the lower
significant location.
 Continue till you find a pair of bits that are not equal.

 If the value of the bit in A is 1 then A > B if the bit in B is 1

then A < B
 For a 4-bit magnitude comparator remember that the output

of the equality XNOR gates are x3, x2, x1, x0, the Boolean
expression of A > B and A < B are:
(A > B) = A3B3’ + x3A2B2’ + x3x2A1B1’ + x3x2x1A0B0’
(A < B) = A3’B3 + x3A2’B2 + x3x2A1’B1 + x3x2x1A0’B0

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 4-bit magnitude
comparator.
 Note that the
design is
implemented using
the fundamental
logic gates (AND,
OR, NOT) only (no
XOR gates are
used)

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Additional Notes
 This lecture covers the following
material from the textbook:
 Chapter 4: Sections 4.5 and 4.8

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