Digital Logic

Lecture 11

Sequential Circuits and Storage

Elements

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Computer Engineering Department
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Outline
 Introduction.
 Sequential circuits.
 Memory Elements.
 Latches:
 SR latch

 D latch

 Flip-flops:
 SR flip-flop

 D flip-flop

 JK flip-flop

 T flip-flop

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Introduction
 Till now we have dealt with combinational logic
circuits in which there are no feedback paths and
storage elements.
 In such circuits the output depends only on the
current combination of the inputs.
 In this chapter we will study the second type of logic
circuits which is called sequential logic circuits.
 Basically this chapter introduces the following:
 Basic memory elements in digital systems.
 Analysis and design of synchronous sequential circuits.

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Sequential Circuits I
 Sequential circuit consists of feedback path and
several memory elements.
 Sequential circuit = Combinational Logic
+ Memory Elements

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Sequential Circuits II
 The binary value stored in the storage
elements define the current state of the
sequential circuit.
 The current state beside the external inputs
values define the next state of the circuit that
will be stored in the storage elements.
 Also, the external inputs determine when to
change the state of the circuit.

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Sequential Circuits III
 There are two types of sequential circuit
 Synchronous:
 Output changes at certain time (there is a clock applied
to the circuit).
 Stable: can be classified into monostable and bistable
circuits.
 Asynchronous:
 Output changes at any time based on the inputs signals
or values.
 The output depends only on the propagation delay of the
inputs to reach the output.
 Can be unstable.
 In this course we will study synchronous
sequential logic circuits mainly.
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Sequential Circuits IV
 Bistable logic devices are latches and
flip-flops.
 Latches and flip-flops differ by the
method used to change stable
condition.

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Memory Elements I
 Memory element device can remember a value for a certain period of
time, or change value based on the input instructions.
 Two basic types:
 Latches: transparent while the internal memory is being set from
the data input.
 Flip-flops: not transparent-reading input value and changing output
are two separate events.
 Commands for latches include set and reset commands mainly (also,
there is no change command).

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Memory Elements II
 Flip-flop is a memory element which change its
condition based on clock signal.
 Clock is a square waveform. The clock pulses
determine when computational activity (next state of
the system) will occur.
 The output of this activity is function of the external
inputs and the current state (sometimes called
previous state) of the system.

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Memory Elements III
 There are two types of trigger/activator
 Pulse triggered (asynchronous logic circuits)
 Edge triggered (synchronous logic circuits)
 Pulse triggered
 Latch
 ON when clock is at 1 level, OFF when clock is at 0 level (or
in the opposite)
 Edge triggered
 Flip-flop
 Positive edge triggered (ON when clock changes from 0 to
1, OFF=other time)
 Negative edge triggered (ON when clock changes from 1 to
0, OFF=other time)

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Latches
 Latches are said to be level sensitive devices.
 They are asynchronous logic circuits since
they are pulse triggered.
 We will study since they are the basic building
blocks of flip flops.
 Two types of latches:
 Set-Reset Latches (SR Latches).
 Data Latches (D Latches).

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SR Latches
 Output has complement: Q and Q’
 When Q HIGH, latch in SET condition
 When Q LOW, latch in RESET condition
 Two types:
 Active high (called SR latch).
 Active high (called S’R’ latch).
low

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Active High SR Latch I
 For SR with active high input (also known as
NOR gate latch)
 R = HIGH (and S=LOW) – RESET condition
 S = HIGH (and R=LOW) – SET condition
 Both LOW – no condition change
 Both HIGH - Q and Q’ becomes LOW (invalid)
(forbidden).
 Constructed by Cross-coupling of two NOR
gates gives the S – R Latch.
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 Active High SR Latch II
Time R S Q Q Comment
0 0 0 1 Initially latch is reset R (reset)
0 1 1 0 “Set” Q to 1 Q
0 0 1 0 Now Q “remembers” 1
1 0 0 1 “Reset” Q to 0
0 0 0 1 Now Q “remembers” 0
1 1 0 0 Both go low (invalid) S (set) Q
0 0 ? ? Unstable!

You can fill the above table starting

with the latch is initially set, Q = 1

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Active Low S’R’ Latch I
 For all S’R’ with active LOW input (also known
as NAND gate latch)
 R = LOW (and S=HIGH) – RESET condition
 S = LOW (and R=HIGH) – SET condition
 Both HIGH – no condition change
 Both LOW - Q and Q’ becomes HIGH (invalid 
forbidden).
 Constructed by Cross-coupling of two NAND
gates gives the S – R Latch.
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 Active Low S’R’ Latch II
S (set)
Q
Time R S Q Q Comment
1 1 0 1 Initially the latch is in reset state

1 0 1 0 “Set” Q to 1 Q
R (reset)
1 1 1 0 Now Q “remembers” 1
0 1 0 1 “Reset” Q to 0
1 1 0 1 Now Q “remembers” 0
0 0 1 1 Both go high (invalid)
1 1 ? ? Unstable!

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Clocked S-R Latch
 Also called SR latch with enable line.
 Adding two NAND gates to the basic S-R
NAND latch gives the clocked S–R latch.
 Has a time sequence behavior similar to the
basic S-R latch except that the S and R inputs
are only observed when the line En is high.
 “En” denotes an enable line. Sometimes it is
called “C” which stands for control or clock.
 Depends on the state of “En” whether they
are active high or active low you determine
when the latch is ON or OFF.
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Clocked S-R Latch Design

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 D Latch I
 D latch is constructed by adding an inverter to the SR
Latch and combine both inputs as shown below.
 Note that there are no “indeterminate” states!

Q D Q(t+1) Comment
0 0 0 No change D Q
0 1 1 Set Q
1 0 0 Clear Q
1 1 1 No Change Q

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D Latch II
 Also called the transparent latch since
the output (next state) is the same as
the input on the D.
 Mainly used for temporary storage of
binary data (each latch can store one
bit).

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Clocked D Latch
 Similar to SR latch add two NAND gates
and an En (enable line) input to the D –
latch to get the clocked version.
 When EN is HIGH
 D=HIGH – latch is in SET
 D=LOW – latch is in RESET
 Therefore, when EN is HIGH, Q will
follow input D.

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Clocked D Latch Design

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Latches Block Diagrams

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Flip Flops I
 Flip Flops are said to be edge sensitive devices.
 They are synchronous logic circuits since they are
edge triggered (respond only during the signal
transition of the clock).
 More stable than latches (avoid the problem of the
unpredicted operation of latches when there is a
common clock for the whole circuit).
 Latches are the basic building blocks of flip flops.
 Two ways to construct flip flops from latches:
 Using two latches in a special configuration (master-slave
configuration)  we will study this type only.
 Build a flip flop that is active at the transition of the clock
pulse and it is disabled for the rest of the clock pulse.

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Flip Flops II
 Three types of Flip Flops:
 D flip flops.
 JK flip flops.
 T flip flops.
 The D flip flop is the main building block of all other
flip flops.
 Each flip flop has its name according to the inputs it
has. For example, JK flip flop has two inputs named
as J and K.
 We will not study the internal implementation of
these flip flops. We are mainly interested in their
operation and behavior.

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Flip Flops III
 Flip flops parameters:
 Setup time: minimum time during which the flip
flop input must not be changed before the clock
transition.
 Hold time: minimum time during which the flip
flop input must not be changed after the +ve or –
ve transition of the clock (-ve or +ve depends on
the flip flop type).
 Propagation delay time: is the interval between
the trigger edge and the stabilization of the output
to a new state.
 Such parameters are defined by the
manufacturer of the flip flop.
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D Flip Flop
 Data flip flops (D flip flops) are the most
widely used.
 Called “transparent Flip Flop” since the next
state of the output is the same as the input
on the D line.
 Basic building block of all other types of flip
flops.
 Has the D latch as its basic building block.
 Have only two states:
 Set  Q = 1 when D = 1.
 Reset  Q = 0 when D = 0.
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 D Flip Flop Construction –
Master Slave Configuration I
 D-flip flop construction from two clocked D
latches and an inverter gate using the master
slave configuration to make the latches edge
triggered (the basic requirement for flip flops).

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 D Flip Flop Construction –
Master Slave Configuration II
 As shown in the previous figure, the first latch is called the
master whereas the second one is called the slave.
 The slave latch is enabled when the clock is 0.
 The master latch is enabled when the clock is at level 1.
 D flip flop operation:
 Clock at level 1  master enabled and slave disabled, output of
master equals its input D. However, the slave output do not change
since it is disabled and its equal the previous state.
 Clock at level 0  master disabled and so no change on its output
which is the input for the slave latch. The slave is enabled so Q
equals to the output of the master latch.
 As you see the new state of the output Q appears when
clock changes from 1 to 0 which means that we have
constructed a –ve edge triggered D flip flop.
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D Flip Flop Block Diagrams

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Characteristic Table and
Equation of D Flip Flop I
 Characteristic table describes the operation of a flip
flop (or any sequential circuit) in tabular form, in
which you find the following:
 Present state Q(t): which is the present output on the flip
flop before applying the clock transition.
 External inputs: such as D, J and K, T, etc.
 Next state Q(t+1): which the output on the flip flop after
applying the clock transition.
 Clock transitions are implied.
 Characteristic equation: describes the operation of
the flip flop (or any sequential circuit) algebraically
(using a Boolean expression). Mainly, it determines
the next state in terms of the present state and the
external inputs.
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Characteristic Table and
Equation of D Flip Flop II
 Characteristic table

D Q(t+1)
0 0 Reset
1 1 Set

 Characteristic equation
Q(t+1) = D

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JK Flip Flop
 Constructed from D flip flop and
external gates.
 Have two inputs named as J and K.
 Have three states at its output:
 Set  Q = 1 when J = 1 and K = 0.
 Reset  Q = 0 when K = 1 and J = 0.
 Complement its output  when J = 1 and
K = 1.

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JK Flip Flop Block Diagrams
 +ve edge triggered  -ve edge triggered
JK flip flop JK flip flop

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 Characteristic Table and
Equation of JK Flip Flop
 Characteristic table J K Q(t+1)
0 0 Q(t) No change
0 1 0 Reset
1 0 1 Set
1 1 Q’(t) Complement
 Characteristic or Toggling
equation:
Q(t+1) = JQ’ + K’Q

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T Flip Flop
 Called “Toggle Flip Flop” and
“Complementing Flip Flop”.
 Can be constructed form either:
 JK flip flop have JK connected together.
 Or from a D flip flop as shown in the figure
in the next slide.
 Always complementing its output.
 Useful for the design of binary counters.

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 T Flip Flop Block Diagram

Also, there is –ve edge triggered T flip flop.

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Characteristic Table and
Equation of T Flip Flop
 Characteristic table
T Q(t+1)
0 Q(t) no change
1 Q’(t) Toggling

 Characteristic equation:
Q(t+1) = TQ’ + T’Q

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Direct Inputs I
 When the power is turned off the state of the
flip flop is unknown.
 So, you cannot work with such flip flop till its
state is known.
 To solve such problem, flip flops are provided
with asynchronous inputs that brings the flip
flop to a known state regardless of the clock
and the current state of the flip flop.
 Such inputs are called direct inputs.

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Direct Inputs II
 Two types of direct inputs:
 Clear or direct reset: when active forces the flip
flop to reset  Q = 0.
 Preset or direct set: when active forces the flip
flop to set  Q = 1.
 Such direct inputs can be active low or active
high (see if there is a bubble or not).
 All flip flops can have direct inputs.
 As an example we will explore D flip flop with
direct reset input.
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Direct Inputs III

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Additional Notes
 This lecture covers the following
material from the textbook:
 Chapter 5: Sections 5.1 - 5.4

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 Latches are asynchronous (transparent)
 The output changed if the input is changed
 Flip flops are synchronous (not transparent)
 The input as well as the clock (enable) must be changed

 Design D latch using NOR

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