INSTRUCTIONS & ITS TYPES

By
SHIVANI AGARWAL
Department of Computer Science & Engineering
IMS Engineering College, Ghaziabad
 Register Transfer language
A digital computer system exhibits an interconnection of
digital modules such as registers, decoders, arithmetic
elements, and Control logic.
These digital modules are interconnected with some
common data and control paths to form a complete digital
system.
Moreover, digital modules are best defined by the registers
and the operations that are performed on the data stored in
them.
The operations performed on the data stored in registers
are called Micro-operations.
MICROINSTRUCTIONS &
OPERATIONS
 R1: A+B
 R1 M[A] + M[B] MICRO OPERATION
 R1 M[A] + M[B] ,R2  R1 MICRO
INSTRUCTION

A micro-operation is an elementary operation performed

on the information stored in one or more registers, the
result of the operation may replace the previous binary
information or may be transfer to another registers.
Examples of micro operations are:-
shift ,count, clear and load
 Register Transfer language
The Register Transfer Language is the symbolic representation
of notations used to specify the sequence of micro-operations
and transfer the result of the operation to the same or another
register.
The internal hardware organization of a digital system is best
defined by specifying:
The set of registers and the flow of data between them.
The sequence of micro-operations performed on the data which
are stored in the registers.
The control paths that initiates the sequence of micro-operation
Computer registers are designated by capital letters:-
MAR ,MBR IR
In a computer system, data transfer takes place between
processor registers and memory and between processor
registers and input-output systems. These data transfer can
be represented by standard notations given below:
Notations R0, R1, R2..., and so on represent processor
registers.
The addresses of memory locations are represented by
names such as LOC, PLACE, MEM, etc.
Input-output registers are represented by names such as
DATA IN, DATA OUT and so on.
The content of register or memory location is denoted by
placing square brackets around the name of the register or
memory location.
Types of instruction
Data transfer instruction
Data manipulation instruction
Program control instruction
 Data transfer instruction
The data transfer instructions are used to transfer data from
one location to another. This transfer of data can be either
from register to register, register to memory or memory to
register. It is important to note here that the memory to
memory transfer of data directly is not possible.
Following are some instructions that are used for data
transfer purpose:
MOV LOAD
PUSH XCHG
POP IN OUT
 STORE
 Data manipulation instruction

Data manipulation have arithmetic operations, logical

operations and shift operations.
Arithmetic operations :-
1. ADD 5. INC
2. SUB 6. DEC
3. MUL 7. ADD With Carry
4. DIV 8. Subtract with borrow 9. Negate
Logical Operations:-
1. Compliment (COM) 4. Ex-OR 7. Set carry
2. CLEAR(CLR) 5. Clear Carry 8. Compliment carry
3. Logical AND 6. Logical OR 9.Enable
Interrupt/Disable
 COM 0101
 1111
 CLR 1010
 0000
 LOGICAL AND 1010
 0000
 LOGICAL OR 1010
 1111
 10101010 1010
 0001AND
 0000 1011
 0001 00
Data manipulation instruction

Shift operations:-
1. Logical Shift left
2. Logical shift right
3. Arithmetic shift left
4. Arithmetic shift right
5. Rotate left
6. Rotate right
7. Rotate left with carry
8. Rotate right with carry
Program Control Instructions
When CPU process the data from consecutive memory
locations so each time one instruction is fetched from
memory and the program counter is incremented.
It has two types of instructions:-
1) Unconditional
2) Conditional
Unconditional:- An unconditional branch instruction
means control proceeds the next instruction in
sequence.
Conditional:- A conditional branch instruction means
control proceeds the next instruction when the
condition met .
Program Control Instructions
JUMP
SKIP
BRANCH
CALL
RETURN
COMPARE
 General Purpose Register
Organization
Generally CPU has seven general registers. Register
organization show how registers are selected and how data
flow between register and ALU. A decoder is used to
select a particular register. The output of each register is
connected to the multiplexers to form the two buses A and
B. The selection lines in each multiplexer select the input
data for the particular bus.
The A and B buses form the two inputs of an ALU. The
operation select lines decide the micro operation to be
performed by ALU. The result of the micro operation is
available at the output bus. The output bus connected to the
inputs of all registers, thus by selecting a destination register
it is possible to store the result in it.
General Purpose Register
Organization
General Purpose Register
Organization

SEL A SELB SELC SELD Or

OPR
010 001 011 00010
General Purpose Register
Organization
A BUS Organization for 7 CPU registers ,one input and the
output of each register is connected to the MUX as A and B.
The selection lines in each MUX select one register at a time.
A and B buses from the inputs to the common ALU for
operations.
Operation select bits are defined as OPR.
The result of the micro operation is load by the selector A
that is SELA.
Decoder activates one of the register to load the output.
For example:- R2 R1+ R3
SEL A SELB SELC SELD Or
OPR
 Questions
A bus organization has 16 registers ,each register has 32
bits. An ALU and a destination decoder so find out :-
a) How many mux are there in BUS A.
b) What is the size of each mux
c) How SEL inputs are needed for MUX A and MUX B.
d) How many inputs and outputs are in decoder.
e) How many inputs and outputs are in ALU for data.
f) Formulate a control word for system assuming that the
ALU has 35 operations.
g) Design a control word with symbolic and binary
representation:-
h) a) R1 R2+R3 b) R1 R2- R3
Questions
a) 32
b) 16* 1
c) 4,4
d) 4*16
e) 64 inputs ,32 outputs
f) 4 bit 4 bit 4 bit 6 bit

SEL A SELB SELC OPR

0001 0010 0011 000000
0001 0010 0011 000001
Questions
A bus organization has 20 registers ,each register has 35
bits. An ALU and a destination decoder so find out :-
a) How many mux are there in BUS A.
b) What is the size of each mux.
c) How SEL inputs are needed for MUX A and MUX B.
d) How many inputs and outputs are in decoder.
e) How many inputs and outputs are in ALU for data.
f) Formulate a control word for system assuming that the
ALU has 35 operations.
g) Design a control word with symbolic and binary
representation:-
h) a) R6 R1/R3
MUX
Demux(de-multiplexer)
1:2n
Selection lines n

I S0 S1 Y0 Y1 Y2 Y3
I 0 0 Y0 0 0 0
I 0 1 0 Y1 0 0
I 1 0 0 0 Y2 0
I 1 1 0 0 0 Y3

Y0=IS0’S1’
Y1=IS0’S1 Y2=IS0S1’ Y3 IS0S1
 Instruction Format
Computer perform task on the basis of instruction provided.
An instruction in computer comprises of groups called
fields. These field contains different information as for
computers every thing is in 0 and 1 so each field has
different significance on the basis of which a CPU decide
what to perform. The most common fields are:
Operation field which specifies the operation to be
performed like addition.
Address field which contain the location of operand, i.e.,
register or memory location.
Mode field which specifies how operand is to be founded.
 Instruction Format
Generally CPU organization are of three types on the basis of
number of address fields:
General register organization
Single Accumulator organization
Stack organization
Three Address Instructions :-This has three address field to
specify a register or a memory location. These instructions
make creation of program much easier but it does not mean
that program will run much faster because now instruction
only contain more information but each micro operation
(changing content of register, loading address in address bus
etc.) will be performed
Op-code
in one cycle only.
Destination Source1 Source2
Instruction Format
Expression: X = (A+B)*(C+D)
R1, R2 are registers and M[] is any memory location.
X = (A+B)*(C+D)
ADD R1, A, B [ where R1=A+B] R1 = M[A] + M[B]
ADD R2, C, D [ where R2=C+D] R2 = M[C] + M[D]
MUL X, R1, R2 M[X] = R1 * R2
Advantage:- It result in very short program.
Disadvantage:- it required too many bits to specify this
format.
 Instruction Format
Two Address Instructions :- This is common in
commercial computers. Here two address can be specified in
the instruction.
In this format we use move instruction to transfer the
registers from the memory or processor register.

Op-code Destination Source

Instruction Format
Expression: X = (A+B)*(C+D)
R1, R2 are registers and M[] is any memory location.
MOV R1, A R1  M[A]
ADD R1, B R1 R1 + M[B]
MOV R2, C R2  C
ADD R2, D R2 R2 + M[D]
 MUL R1, R2 R1  R1 * R2
MOV X, R1 M[X]  R1
 Instruction Format
One Address Instructions –
This use a implied ACCUMULATOR register for data
manipulation. One operand is in accumulator and other is in
register or memory location. Implied means that the CPU
already know that one operand is in accumulator so there is
no need to specify it.
It can be used to calculate the data from source to
accumulator and transfer the data from accumulator to
accumulator.
In this format we use load and store mnemonic for
calculation, where load mnemonic is used to load the value
of operand in the accumulator and store is used to store the
data from accumulator.
Instruction Format
LOAD A AC M[A]
ADD B AC AC + M[B]
STORE T M[T] AC
LOAD C ACM[C]
ADD D AC AC + M[D]
MUL T AC AC * M[T]
STORE X M[X]AC
 Instruction Format
zero Address Instructions
Expression: X = (A+B)*(C+D)
Post fixed : X = AB+CD+*
TOP means top of stack and M[X] is any memory location
PUSH A TOP = A
PUSH B TOP = B
ADD TOP = A+B
PUSH C TOP = C
PUSH D TOP = D
ADD TOP = C+D
MUL TOP = (C+D)*(A+B)
POP X M[X] = TOP
 Question

DIV X,R1,R2 M[X] R1/R2

 Question
TWO ADDRESS FORMAT :-
Question
ONE ADDRESS FORMAT:-
 Question

DIV TOS (A+B*C)/(D-E*F+G*H)

POP X M[x]=TOP
 Question
Q1:-A computer has 32 bit instruction format ,12 bit
addresses are used if there are 250(2 address instruction)
then how many 1 address instruction can be formulated?

Q2:- A computer has 42 bit instruction format ,14 bit

addresses are used if there are 300(2-address instruction)
then how many 1-address instruction can be formulated?
 Addressing Modes
The term addressing modes refers to the way in which the
operand of an instruction is specified. The addressing
mode specifies a rule for interpreting or modifying
the address field of the instruction before the operand is
actually executed. Addressing mode has nothing to do with
the opcode part. It focuses on presenting the operand’s
address in the instructions.
That define the way through which the operands are chosen
during the program execution is dependent on addressing
mode of the instruction. It specifies a rule for modifying the
address field of the instruction before operand is actually
reference.
Mode field is used to locate the operands needed for the
 Addressing Modes
Types of Addressing Modes:-
Implied Addressing Mode
Immediate Addressing Mode
Register Addressing Mode
Register Indirect Addressing Mode
Direct Addressing Mode
InDirect Addressing Mode
Relative Addressing Mode
Index Addressing Mode
Auto Increment Mode
Auto Decrement Mode
 Addressing Modes
Effective Address (EA):Effective address is the address of
the exact memory location where the value of the
operand is present.

OP-CODE MODE OPERAND

Implied Mode:- In this mode ,the operands are specified

implicitly in the definition of the instruction.
Immediate Mode:- In this mode, the operand is directly
provided as constant. An immediate mode instruction has an
operand field rather than the address field. For example: ADD
R1,7, which says Add 7 to contents of register R1.
Addressing Modes
Register Mode:-In this mode the operand is stored in the
register and this register is present in CPU. The instruction
has the address of the Register where the operand is stored.
 Addressing Modes
Register Indirect Mode:-In this mode, the instruction
specifies the register whose contents give us the address of
operand which is in memory. Thus, the register contains
the address of operand rather than the operand itself.
 Addressing Modes
Direct addressing mode:-The address field of the
instruction contains the effective address of the operand.
Only one reference to memory is required to fetch the
operand. It is also called as absolute addressing mode.
 Addressing Modes
In-Direct addressing mode:- In this addressing mode,
The address field of the instruction specifies the address
of memory location that contains the effective address of
the operand.
Two references to memory are required to fetch the
operand.
 Addressing Modes
Relative Addressing Mode:-In this mode the content of
PC is added to the address part of the instruction to obtain
the effective address whose position in memory is relative
to the address of next instruction i.e.
EA= PC + delta + Address
Index Mode:- In this mode, the content of index register
added to the address part of the register to obtain the
effective address.
EA=XR+ address of Instruction
 Addressing Modes
Auto increment or Auto decrement Mode:- In this
mode ,In auto-increment addressing mode once the content
of the register is accessed by the instruction the register’s
content is incremented to refer the next operand.
EA=X+1
In this mode, In auto-decrement addressing mode the
content of the register is decremented initially and then the
decremented content of the register is used as effective
address.
EA=X-1
Question
A 2 word instruction at address 200 and 201 is a load
to accumulator. This instruction with in address field
500,PC has the value 200 for fetching this instruction,
the content of register R1 is 400 and index register is
100 and the other memories of addresses are:-
1) address 399 with Memory 450
2) address 400 with Memory 700
3) address 401 with Memory 520
4) address 500 with Memory 800
5) address 600 with Memory 900
6) address 702with Memory 325
7) address 800 with Memory 300
Question
So find out EA and Operand value by using:-
Immediate Addressing Mode
Register Addressing Mode
Register Indirect Addressing Mode
Direct Addressing Mode
InDirect Addressing Mode
Relative Addressing Mode
Index Addressing Mode
Auto Increment Mode
Auto Decrement Mode
Question
A 1 word instruction at address 300 that is a ADD to
accumulator. This instruction with in address field
450,PC has the value 300 for fetching this instruction,
the content of register is 650 and index register is 200
and the other memories of addresses are:-
1) address 649 with Memory 250
2) address 650 with Memory 700
3) address 651 with Memory 800
4) address 450 with Memory 200
5) address 800 with Memory 400
6) address 1000with Memory 900
7) address 1050 with Memory 600
Question
Q:- The memory unit of a computer has 256k words of 32
bit each. The computer has an instruction format with
four fields:-
a) Op-code
b) Mode to specify one of 7 address mode
c) Register address to specify one of 60 processors
register
d) memory address field
So design the instruction format and the number of
field in each bit if the instruction is in 1-address format.
Question
Q:-The memory unit of a computer has 1024k words of 128
bit each. The computer has an instruction format with
five fields:-
a) Op-code
b) Mode to specify one of 10 address mode
c) Register address to specify one of 48 processors register
d) memory address field
e) A branch address field to specify one of 15 branches
So design the instruction format and the number of field
in each bit if the instruction is in 2-address format.
 Stack Organization
The computers which use Stack-based CPU Organization
are based on a data structure called stack. The stack is a
list of data words. It uses Last In First Out
(LIFO) access method which is the most popular access
method in most of the CPU.
The register that holds the address for the stack is called
a stack pointer (SP) because its value always points at the
top item in the stack.
Stack Organization divided in to two parts:-
1) Register Stack
2) Memory stack
 Register Stack
Register Stack A stack can be placed in a portion of a
large memory or it can be organized as a collection of a
finite number of memory words or registers. Figure 3
shows the organization of a 64-word register stack. The
stack pointer register SP contains a binary number whose
value is equal to the address of the word that is currently
on top of the stack. Three items are placed in the stack: A,
B, and C, in that order. Item C is on top of the stack so that
the content of SP is now 3.
There are two operations in a stack:-
1) PUSH
2) POP
Register Stack
 Register Stack
 Initially, SP is cleared to 0, EMTY is set to 1, and FULL is cleared to 0, so
that SP points to the word at address 0 and the stack is marked empty and not
full. If the stack is not full (if FULL = 0), a new item is inserted with a push
operation.
 The push operation is implemented with the following sequence of micro-
operations:-
SP ← SP + 1 Increment stack pointer
M[SP] ← DR Write item on top of the stack
If (SP = 0) then (FULL ←1) Check if stack is full
EMTY ← 0 Mark the stack not empty
 The stack pointer is incremented so that it points to the address of the next-
higher word. A memory write operation inserts the word from DR into the top
of the stack. Note that SP holds the address of the top of the stack and that
M[SP] denotes the memory word specified by the address presently available
in SP.
 Register Stack
POP operation:-
DR ← M[SP] Read item from the top of stack
SP ← SP - 1 Decrement stack pointer
If (SP = 0) then (EMTY ← 1) Check if stack is empty
FULL ← 0 Mark the stack is not full
 The top item is read from the stack into DR . The stack pointer is then
decremented. If its value reaches zero, the stack is empty, so EMTY is set to
1.
 This condition is reached if the item read was in location 1. Once this item
is read out, SP is decremented and reaches the value 0, which is the initial
value of SP.
 Memory Stack
A stack can exist as a stand-alone unit or can be
implemented in a random-access memory attached to a
CPU. The implementation of a stack in the CPU is done by
assigning a portion of memory to a stack operation and
using a processor register as a stack pointer.

Diagram shows a portion of computer memory partitioned

into three segments: program, data, and stack. The program
counter PC points at the address of the next instruction in the
program. The address register AR points at an array of data.
Memory Stack
 Memory Stack
We assume that the items in the stack communicate with a
data register DR . A new item is inserted with the push
operation as follows:
SP ← SP – 1
 M[SP] ← DR
The stack pointer is decremented so that it points at the
address of the next word. A memory write operation inserts
the word from DR into the top of the stack. A new item is
deleted with a pop operation as follows:
DR ← M[SP]
SP ← SP + 1
 Bus Arbitration
Bus Arbitration is a process which decides among a number
of devices requesting to use the system bus which one to
grant across of bus.
Bus Arbitration refers to the process by which the current
bus master accesses and then leaves the control of the bus
and passes it to the another bus requesting processor unit.
The controller that has access to a bus at an instance is
known as Bus master.
 Bus Arbitration
A conflict may arise if the number of DMA controllers or
other controllers or processors try to access the common bus
at the same time, but access can be given to only one of those.
Only one processor or controller can be Bus master at the
same point of time.
 To resolve these conflicts, Bus Arbitration procedure is used,
to coordinate the activities of all devices requesting memory
transfers.
The selection of the bus master must take into account the
needs of various devices by establishing a priority system for
gaining access to the bus. The Bus Arbiter decides who
would become current bus master.
Bus Arbitration
There are two approaches to bus arbitration:
1) Centralized
2) Distributed
3) Centralized:- A single hardware device i.e. CPU
control or DMA controller is used to act as a arbitrator
to decide among a no of devices that which one will
use the bus firstly. There are 3 types of methods:-
a) Daisy chaining
b) Polling method
c) Independent request
Centralized Bus Arbitration
Daisy Chaining:- It is a simple and cheaper method
where all the bus masters use the same line for making
bus requests. The bus grant signal serially propagates
through each master until it encounters the first one
that is requesting access to the bus. This master blocks
the propagation of the bus grant signal, therefore any
other requesting module will not receive the grant
signal and hence cannot access the bus.
 Daisy Chaining:-
 In this method, all requesting components are attached serially on to the bus.
 All the bus units are connected to BUS REQUEST line.
 When activated, it indicates that one or more devices are requesting to use
the bus.
 Bus Controller responds to a BUS REQUEST only if BUS BUSY is
inactive. When bus control is given to requesting device, it enables its
physical bus connection and activates BUS BUSY.
 When the 1st requesting device gets control of the bus and recievies BUS
GRANT signal, it blocks further propagation of signals, activates BUS
BUSY and begins to use
 When a non requesting device receives BUS GRANT signal, it forwards the
signal to next device.
 Thus if two devices simultaneously request bus access, the device that is
closer to the bus controller receives BUS GRANT and receives the bus
control.
 Means the devices that are closed to the bus controller are of higher priority
Daisy Chaining:-
 Advantages –
1)Simplicity and Scalability.
2) The user can add more devices anywhere along the
chain, up to a certain maximum value.
 Disadvantages –
1)The value of priority assigned to a device is depends on
the position of master bus.
2)Propagation delay is arises in this method.
3)If one device fails then entire system will stop working.
Centralized Bus Arbitration
(ii) Polling or Rotating Priority method –
In this, the controller is used to generate the address for
the master(unique priority), the number of address lines
required depends on the number of masters connected in
the system. For example, if there are 8 masters connected
in a system at least 3 address lines are required. The
controller generates a sequence of master address. When
the requesting master recognizes its address, it activates
the busy line and begins to use the bus.
Polling or Rotating Priority method
Working:-
 This method replaces the BUS GRANT line of daisy chain method with a
set of poll count lines that are connected directly to all devices on the bus.
 Devices request access to the bus via a common BUS REQUEST line.
 Bus controller generates a sequence of numbers on the poll count lines.
 Each device compares these numbers as their device address already
assigned to them.
 When a requesting device finds that its address matches the numbers on
the poll-count lines, the device activates BUS BUSY.
 The bus controller responds by terminating the polling process and the
device connects to the bus.
Polling or Rotating Priority method
Polling or Rotating Priority
method
Advantage:-
1) Reduced cost due to common bus
2) Entire system does not fail in case one module
fails.
3) Flexible priority
Disadvantage:-
1) Poll count lines increases as number of devices
increases.
Independent Request
There are separate BUS REQUEST and BUS
GRANT lines for every device that are sharing
bus.
In this, bus controller has the capability of
immediate identifying all the requesting devices.
Bus controller responds rapidly to the request by
determining the highest priority device that has
sent the bus request.
This priority is programmable and is
predetermined.
Independent Request
Independent Request
Advantage:-
1)Fast arbitration
2)Speed independent of no. of devices connects.
Disadvantage:-
1) Hardware cost is high as large no. of control lines are
required.
Distributed method
No central authority.
all the devices participate in the selection of the next
bus master.
When one or more devices request control of the bus,
they assert the start arbitration signal and place their 4-
bit identification numbers on arbitration lines through
ARB3.
Each device compares the code and changes its bit
position accordingly.
It does so by placing a 0 at the input of their drive.
The distributed arbitration is highly reliable because
the bus operations are not dependant on devices.