ARM PROGRAMMING MODES

AND REGISTER SET

OUTLINE
 ARM Data Types
 ARM Processor Modes
 ARM Operating States
 ARM Registers
 ARM Exceptions
 Memory and memory-mapped I/O
 PDF created
ARM DATA TYPE
ARM processor support the following data
types:
 Byte: 8 bits

 Halfword: 16 bits

- Halfwords must be aligned to two-byte boundaries

 Word: 32 bits

Words must be aligned to four-byte boundaries

ARM DATA TYPE
ARM allow addresses to be 32 bits long
 An address refer to a byte, not a word

 Word 0 is at location 0

 Word 1 is at location 4

 PC is incremented by 4 in sequential access

 Can be configured at power-up to address the

bytes in a word in either little-endian or bitendian mode

BYTE ORGANIZATION WITHIN AN ARM
WORD
 Little-endian mode
 The lowest-order byte residing in the low-order bits of
the word
 Big-endian mode

 The lowest-order byte stored in the highest bits of the

word
ARM PROCESSOR MODES
 User mode:
a normal program execution state
 FIQ (Fast Interrupt Request) mode:

for supporting a specific data transfer or channel processing

 IRQ (Interrupt ReQuest) mode:

for general purpose interrupt handling

 Supervisor mode:

a protected mode for the operating system

 Abort mode:

entered when a data or instruction pre-fetch is aborted

 System mode:

a privileged user mode for the operating system, for example,

implement reentrant interrupt handler
 Undefined mode:

entered when an undefined instruction is executed

ARM OPERATING MODES
Operating mode changes
 Can be controlled by software.

 Can also be caused by external interrupts or exception

processing
 Most application programs execute in user mode.

 Privileged modes (the modes other than User mode)

 Are entered to service interrupts or exceptions, or to

access protected resources.
 Exception mode (the privileged mode other than the
system mode)
 Entered when specific exceptions occur

 Each has some additional registers to avoid corrupting

 User mode state when the exception occurs

System mode
 Not entered by an exception

 Have exactly the same registers available in User mode

 However, it is a privileged mode and can access any

system resources
ARM OPERATING STATES
ARM state
 n Executing 32-bit, word-aligned, ARM

 Instructions

THUMB state
 n Executing 16-bit, half-word aligned THUMB

 Instructions

These states can be switched by software or

by exception processing
ARM EXCEPTIONS
 An exception arises when the normal flow of
program execution is interrupted
 The processor state just prior to handling the

 exception must be preserved

 The program flow can be resumed when the exception

routine is completed
 To process exceptions, the ARM processor uses the

banked core registers to save the current state

 The old PC value are copied into the R14 (LR) register

 The CPSR contents are copied into the SPSR registers

 To return after handling the exception
SPSR is moved to the CPSR
R14 is moved to the PC (R14)
 When an exception occurs

 Execution is forced to execute from a fixed

memory address corresponding to the type of

execution.
 These fixed addresses are called the exception

vector
ARM EXCEPTION TYPES
 Reset
 Undefined instruction
 Software Interrupt (SWI)
 Prefetch Abort
 Data Abort
 IRQ
 FIQ
 PDF
ARM REGISTERS
o ARM has a total of 37 registers
o 31: general-purpose, 32-bit registers
o r0~r15, r8_fiq~r13_fiq, r14_fiq, r13_irq, r14_irq,
r13_svc, r14_svc, r13_abt, r14_abt, r13_und, r14_und
o 6: status registers
o CPSR
o SPSR_fiq, SPSR_irq, SPSR_svc, SPSR_abt, SPSR_und
o Not all of these registers are always available
o Processor state: ARM or Thumb
o Unbanked registers: r0~r7
o Banked registers: r8~r14
 Unbanked registers (R0-R7)
 Each of the registers refers to the same 32-bit

physical registers in all processor modes

Banked registers (R8-R14)
 The physical register referred to by each of them

depends on the current processor mode

 For example, R8_usr v.s. R8_fiq
REGISTER ORGANIZATION IN ARM
STATES
REGISTER ORGANIZATION IN ARM
STATES
 ARM State General Registrations andProgram Counter
ARM State Program Status Register
ARM REGISTERS
 R8-R12
Have two banked physical registers
 R13-R14

Have six banked physical registers

 By convention
 R13: SP (stack pointer)
 n R14: LR (link register)

In User mode: R14 is used as a link register to store the return

address when a subroutine is made
In the exception handling modes, R14 holds the return address for
the exception
 R15: PC (program counter)
 Incremented by one word for each instruction
 To return from a subroutine
 MOV pc, lr
PSR (PROGRAM STATUS REGISTER)
REGISTER)
The format of CPSR and SPSR are the same
 Called PSR in general

One CPSR (Current Program Status Register)

 Copies of the Arithmetic Logic Unit (ALU) status
flags
 The current processor mode

 Interrupt disable flags

Five SPSR (Saved Program Status Registers)
 Used to store the CPSU when an exception is taken

 One SPSU is accessible in each of the exception-

handling mode
 User mode and System mode do not have an SPSR

because they are not exception handling modes

PSR REGISTER
 Flag field: PSR[31:24], ARM7TDMI only defines four bits
 PSR[31]: N, PSR[30]: Z, PSR[29]: C, PSR[28]: V

 Status field: PSR[23:16], undefined in ARM7TDMI

 Extension field: PSR[15:8], undefined in ARM7TDMI

Control field
 I: PSR[7]: if 1, disable interrupt

 F: PSR[6]: if 1, disable fast interrupt

 T: processor is in ARM state (T=0) or in Thumb state (T = 1)

 Mode: processor mode

STATUS BITS
Top four bits of the CPSR
 N: set when the result is negative in two’scomplement
arithmetic
 Z: set when every bit of the result is zero

 C: set when there is a carry out of the operation

 V: set when an arithmetic operation results in an

overflow
MODE BITS
PSR REGISTERS
MSR AND MRS INSTRUCTIONS
 To access the CPSR and SPSR registers must
use MSR and MRS instructions
 MRS: Move PSR to a General-purpose

Register
 MSR: Move Register to PSR status/flags

 Discussed later in the instruction set section