2 Stage OP design

Design Procedure
1. VCC=5~6V
1
2. Ibias=2uA~3uA(Typ=2.5uA) P1   (rad / s )
3. Gain > 60dB gm6(ro 6 // ro 7)  Cc  (ro 2 // ro 4)
4. Phase Margin > 60deg
5. ICMR=1.1V~4.5V gm6
6. Vout=0.5V~4.5V P2   (rad / s )
7. CL=1pF CL
8. GB=5MHz
gm1 gm2
GB  Av  P1   (rad / s )
Av1   gm1(ro 2 // ro 4) Cc Cc
1
Av 2   gm6(ro 6 // ro 7) Z1  
Cc
(rad / s ) When Rz series with Cc
RzCc 
gm6
Cc  CL 1
If Z1=P2 : Rz  ( )
Cc gm6

I5
Vin (max)  VCC V SG 3VTN 1  VCC   | VTP 3 | VTN 1
W
K ( )3
L
Vin (min)  VDS ( SAT ) V GS 1
 Design Procedure

1. Cc > 0.22CL=0.22pF for 60deg Phase Margin : Cc=0.3pF

2. I5=1.25uA SR=I5/Cc=4.17V/us

W I5 1.25
3. ( )3    1.44
L Kp(VCC  Vin (max) | VTP 3 | VTN 1 ) 2 7.5(5  4.5  0.88  0.72) 2
set W W 3
( ) 3  ( ) 4  1 .5   2
L L 4
4. If GB=5MHz gm1  GB  Cc  9.42(uA / V )
W W gm12 9.422 W W 3
( )1  ( ) 2    2.8 Set ( )1  ( ) 2  2 for Body Effect
L L Kn  I 5 13.65  1.25 L L 4 .5
2
I5 I 1.25
5. VDS ( SAT )  Vin (min)  ( ) 0.5  Vin (min)  ( ( 5 2 )  VTN 1 )  1.1  (  0.72)  0.25
W gm 1 9 . 42
Kn  ( )1
L
W 2I5 2.5 W 4 .5
( )5    2.93 Set ( )5  2  3
L Kn  VDS ( SAT )
2
13.65  0.252 L 3

gm6 gm2
6. P2    2.2  69.08(uA / V ) For 60 o phase margin
CL Cc
W
gm4  2( ) 4 KpI 4  1.5  7.5  1.25  3.75(uA / V )
L
 Design Procedure

In High Frequency, VSG4=VSG6

W W gm6 69.08 13.8 W gm6 69.08 1
(1) ( )6  ( )4  1.5  27.6  2 (
(2) 6)   1 . 5  27 . 6 
L L gm4 3.75 1 L Kp  VDS 6 ( SAT ) 7.5  0.5

gm6 2
I6   11 .5uA
W
I 6  I 7  10uA 2 Kp ( ) 6
set L
Cc  CL 1 1. 3 1
If Z1=P2, Rz  ( )    62.7 K
Cc gm6 0.3 69.06e  12
1 1 gm2 9.42e  6
7.
P1       212Hz
2 gm6(ro 6 // ro 7)  Cc  (ro 2 // ro 4) Av  Cc 23540  0.3e  12

1 gm6 1 69.08e  6
P2       11Mhz
2 CL 2 1e  12
1 1
Z1    11Mhz
2 RzCc  Cc
gm6
2 stage N diff pair OP
 Test Bench for gain and phase margin
VCC 0 5V
Ii1=2.5uA, 3.5uA, 1.5uA VINP=1.1V, 1.12V, 1.08V for TT, FF, SS
 Simulation result in closed loop simulation

TT : Close Loop Gain=87.4dB

phase margin =89.1o
P1=175Hz

GB=4.33MHz
P2=Z1=2.2GB
 Simulation result in closed loop simulation

FF : Close Loop Gain=86.1dB SS : Close Loop Gain=88.7dB

phase margin =82.1o phase margin =93.8o

P1=195Hz P1=154Hz

GB=4.99MHz
GB=4.01MHz
 Test Bench for ICMR
VCC 0 5V VINP=-0.5~6
Ii1=2.5uA, 3.5uA, 1.5uA for TT, FF, SS
Simulation result in ICMR
 Test Bench for SR
VCC 0 5V
VINP pwl 0 0, 20u 0, 20.01u 2.5, 30u 2.5, 30.01u 3.5 60u 3.5, 60.01u 2.5
Ii1=2.5uA, 3.5uA, 1.5uA for TT, FF, SS
Simulation result in SR
Simulation result in SR
 Test Bench for PSRR
VCC 0 5V ac 1V
VINP 0 1.1V Ii1=2.5uA, 3.5uA, 1.5uA for TT, FF, SS
Simulation result in PSRR
 Test Bench for PSRR
VCC 0 5V ac 1V
VVin VCC 0 5
VVinp VINP 0 2.5 ac 1
VVinn VINN VO 2.5 ac 1
VINP 0 1.1V Ii1=2.5uA, 3.5uA, 1.5uA for TT, FF, SS
Simulation result in PSRR