Synthesis to Signoff

(Inputs, outputs, pre and post checks)

Synthesis
• Pre Checks Post Checks
• Check constraints
• RTL and Netlist equivalence
• Check the libraries inserted
• Generation of SDC and UPF
• Analyse (Syntax checks of • Timing checks (unconstrained
RTL)
IOs, IO port delay missing,
• Elaboration
combinational loops etc)
• Check design • Design checks (Floating pins,
multi driven inputs, undriven
inputs/outputs etc)
Inputs
• Technology related:
• Timing information of standard cell, macros, WLM (.lib)

• Design related:
• RTL code (.v),
• Timing constraints(SDC),
• Power intent of the design(UPF),
• Scan related info like scan chain length, scan IO, which flops are to be considered in the scan chains.

• For Physical synthesis, along with above listed files the following files will be also be given:
• Technology file (.tf),
• RC coefficient file(Tlu+)
• Physical abstract view of the cell (LEF/FRAM)
• Floorplan DEF: (block size, shape, metal layers, location of IO ports and macros)
Outputs:
• Netlist
• UPF
• SDC
• Scan DEF (info of scan flops and their connectivity in scan chain)
• Reports:
• report_qor(WNS and TNS for all path group, cell count in details, current design statistics
such as combinational, non combinational and total area, critical path length and its slack)
• report_constraints (violations w.r.t DRVs and all timing checks except noise)
• report_analysis_coverage (how many library specific and user specific checks are tested, met,
violate and utested)
• report_global_timing (FEP, WNS and TNS for both setup and hold timing checks)
• report_timing (point by point info on data paths, their path type, path group, delay and
transition of respective cells used, slack calculation etc)
Floor plan

Inputs of Floorplan Outputs of Floorplan

• Technology file (.tf) Core boundary & area estimated
• Netlist I/O ports placed
• SDC Macro placement done
• Logical library (.lib)
Cell rows created
• Physical library (.LEF)
• TLU+ file Blockages (placement) placed
• Power spec file (UPF) Physical only cells (tap cells, endcap cells, tie cells, spare
cells) placed
Core power ring, straps and rails defined
Floorplan DEF file
Pre checks:
• Library checks
• Design checks
• SDC checks

Post checks
• No I/O ports short
• All I/O ports should be placed in routing grid
• All macros in placement grid
• No macros overlapping
• Check PG connections (For macros & pre-placed cells only)
• All the macros should be placed near the boundary
• There should not be any notches. If unavoidable, proper blockages and halos have to
be added.
• There should be stable voltage with little noise
• No EM and self heating in the block
• Check for utilization
Placement
Inputs of Placement: Outputs of Placement:
• Technology file (.tf)
• Netlist
• SDC
• Logical library (.lib)
• Physical library (.LEF)
• TLU+ file
• Floorplan DEF file
• Congestion report
• Reports for timing, qor, analysis coverage, global
timing, constraint
• Design with all std cells placed in core area
• Log file
• Placement DEF file
Pre checks:
Post checks:
 Check for placement
blockage  Unplaced std cells should be 0
 Don’t use cell list  Cells overlapped should be 0
 Don’t touch cell and  Utilization
net used  No timing issue
 Density  No congestion issue(DRC and
 Optimization detouring)
 Preplaced cells  No data DRVs
(Antenna diode,  Total area after optimization
buffers, special IPs)used  HFNS done
or not
 WLM should be
removed, as at
placement VR are used
for RC
 CTS Outputs:
Inputs :
• Reports for timing, qor, analysis
coverage, global timing,
• Technology file (.tf)
constraint
• Netlist
• Congestion report
• SDC • Insertion delay report
• Logical library (.lib) • report_clock_timing (clock
• Physical library (.LEF) latency, transition, skew)
• TLU+ file • CTS DEF file
• Floorplan DEF file
• Clock specification file: (Max Skew, max
and min Insertion delay, clock
transition, fanout, capacitance, clock
cells, NDR, CTS tree type, CTS
exceptions, list of buffers/inverters,
metal layers, don’t use cells,)
 Post checks:
• Pre checks:
• Check for qor
• Clocks should be balanced
• All the cells should be legalized
• No timing violation
• No timing violation at placement stage
• Insertion delay and skew targets
• No data DRVs should be achieved
• No congestion • DRV targets should be achieved
• Check and qualify • Clock tree exceptions should not
• PG nets routing is done be in the clock tree
• HFNS done • Check for clock constraints (UCR,
multiple clock driving same reg,
exception)
• Check for power and area
optimization
Routing
• Inputs of Routing:
Outputs of Routing:
• Netlist
• Technology file (.tf)
• Physical library (.LEF)
• CTS DEF file
• NDRs
• Routing blockages
• Post Routing db file or DEF file
• Reports for timing, qor, analysis
coverage, global timing,
constraint, clock timing
• Congestion report
• Insertion delay report
• Geometric layouts of all nets
Pre checks: Post Checks:
• Filler cells should be • Check for QoR
added • Check timing violations & timing
• Routing blockages DRVs
should be added • Check for routing congestion
• Metal layers should (opens and shorts)
be defined • Check for DRC, LVS
• Routing region should • Check Antenna violations, EM,
be there ESD
• No timing violation, • Check Area and IR
DRC violation, • Check SI related issues.
Constraint violation • Check for redundant via
till CTS insertion.
Signoff - STA
• Inputs Outputs

• PNR dB file • Saved session(Readme file, cmd log file, lib map, linked
design and loaded libraries, SDC, operating conditions,
• Netlist
parasitics, netlist edits)
• Logical library (.lib)
• Reports for timing, qor, analysis coverage, global timing,
• Physical library (.LEF) constraints, clock timing
• Star RC
• SDC
• Operating conditions.
• Pre checks

• All the design should be linked to the PT tool

• All the libraries should be linked to PT
• Parasitics should be loaded in the tool
• Star RC/ QRC should be used instead of SFEF
• Correct and complete SDC’s should be sourced to the PT
• All the corners should be present for analysis
Post check (timing)

1. Minimum Clock Period 11. Recovery and removal 17. Jitter

12. Non Default Rule (2S,
2. Setup Time Checks 18. Clock Gating Checks
2W)
3. Hold Time Checks 19. Clock Tree Placement
13. Skew check
4. Clock-to-Q Delay
14. Duty cycle 20. Crosstalk (glitch and Crosstalk
5. Clock Domain Crossing
(CDC) Checks 15. Timing exceptions check delta delay)
6. Max delay (Multi clock cycle, False
7. Min delay
path, Case analysis,
8. Max transition
disabling timing arc(very
9. Max capacitance
dangerous ))
10.Max fanout
16. Clock group checks
Signoff physical checks
• DRC (width of poly, spacing between two polies, two wells and two via’s
cuts, continuity of well, min no of cuts a via have)
• LVS (no of instances, ports, nets and types of components of layout
netlist are compared with Verilog netlist and reported as open, short,
extract error (parameter mismatch of the device), compare error
(component mismatch or missing, malformed device)
• ERC (Power/ ground connection of the device, floating substrate/wells)
• Antenna
• EM
• ESD