Programmable peripheral interface 8255

It is a programmable peripheral interface, which means it is a programmable device

used to interface I/O devices with the processor.
• It provides an interface between the processor and the I/O device.

• There are 24 I/O pins which may be individually programmed in 2 groups

of 12 and used in 3 major modes of operation.

• 8255 is connected to 8086 through a data bus and it is connected to the

I/O device through three 8-bit bidirectional I/O ports of 8255(Port A,B,C)
8255 Working
8255 has 3 data ports namely Port – A ( PA ) and PB, PC.

1. Assuming the connected device to be an input device. Initially, the Input device seeks for
permission from PPI so that it can send data.
2. PPI permits Input devices to send data, only when there is no left data in
8255 which should be sent to the 8086 processor. If there is some previous
data left in 8255, which is still not sent to 8086, then it doesn’t permit
Input device.
3. Once 8255 permits input device, data is received and stored in temporary
registers in 8255. Once 8255 holds some data, which should be sent to
8086, then it send signal to 8086.
 4. Whenever 8086 is free to receive the data, then 8086 sends back a signal ,
after that data transmission happens between 8255 and 8086.
5. If 8086 do not becomes free upto long time, which means 8255 has some
value in it which is still not sent to 8086, so 8255 does not permit the Input
device to send any data because the existing data will be overwritten.

All the signal in the above diagrams represented using red curved arrow are known as
handshake signals. This process of data transmission is known as handshaking.
Architecture of 8255
● The parallel input-output port chip 8255 is also called as programmable
peripheral input- output port.
● It has 24 input/output lines which may be individually programmed in two
groups of twelve lines each.
● The two groups of I/O pins are named as Group A and Group B.
● Each of these two groups contains a subgroup of eight I/O lines called as 8-
bit port and another subgroup of four lines or a 4-bit port.
● Group A contains an 8-bit port A(PA0-PA7 ) along with a 4-bit port. C upper.(PC4-
PC7. ) T
● Group B contains an 8-bit port B, containing lines PB0-PB7 and a 4-bit port C
with lower bits PC0- PC3.
● The port C upper and port C lower can be used in combination as an 8-bit port C.
● . All of these ports can function independently either as input or as output ports.
● This can be achieved by programming the bits of an internal register of 8255 called
as control word register (CWR).
The signal description of 8255 are :

ü PA7-PA0: These are eight port A lines that acts as either latched output or buffered input lines

ü PC7-PC4: Upper nibble of port C lines. They may act as either output latches or input buffers
lines. This port also can be used for generation of handshake lines in mode 1 or mode 2.

ü PC3-PC0: These are the lower port C lines, other details are the same as PC7-PC4 lines.

ü PB0-PB7: These are the eight port B lines which are used as latched output lines or buffered
input lines in the same way as port A.
RD: This is the input line driven by the microprocessor and should be low to indicate read
operation to 8255.

ü WR: This is an input line driven by the microprocessor. A low on this line indicates
write operation.

CS: This is a chip select line. If this line goes low, it enables the 8255 to respond to RD
and WR signals, otherwise RD and WR signal are neglected.
ü A1-A0: These are the address input lines and are driven by the microprocessor. These lines
A1-A0 with RD, WR and CS are used for addressing any one of the four registers, i.e. three
ports and a control word register.

ü D0-D7: These are the data bus lines those carry data or control word to/from the
microprocessor.

ü RESET: A logic high on this line clears the control word register of 8255.
Operational Modes of 8255

There are two main operational modes of 8255:

ü Input/output mode

ü Bit set/reset mode

1 Input / Output Mode

There are three types of the input/output mode. They are as follows:
Mode 0

In this mode, the ports can be used for simple input/output operations without
handshaking. If both port A and B are initialized in mode 0, the two halves of port C can
be either used together as an additional 8-bit port, or they can be used as individual 4-bit
ports.

ü O/p are latched.

ü I/p are buffered not latched.

ü Port do not have handshake or interrupt capability.

Mode 1

● To use port A or port B for handshake input or output operation,we initialize that port
in mode 1.Some of the pins of port C function as handshake lines.
● For port B in this mode, PC0, PC1 and PC2 pins function as handshake lines.
● If port A is initialized as mode 1 input port, then, PC3, PC4 and PC5 function as
handshake signals.
● Pins PC6 and PC7 are available for use as input/output lines.
Mode 2

● Only group A can be initialized in this mode.

● Port A can be used for bidirectional handshake data transfer. This means
that data can be input or output on the same eight lines (PA0 - PA7). Pins
PC3 - PC7 are used as handshake lines for port A.
● The remaining pins of port C (PC0 - PC2) can be used as input/output
lines .
Bit Set/Reset (BSR) mode

In this mode only port B can be used (as an output port). Each line of port C (PC0
- PC7) can be set/reset by suitably loading the command word register.
Control Word Format
● The figure shows the control word format in the input/output mode. This mode is
selected by making D7 = '1' .
● D0, D1, D3, D4 are for lower port C, port B, upper port C and port A respectively.
● D2 is used for mode selection for group B (Port B and Lower Port C). When D2 = '0',
mode 0 is selected and when D2 = '1', mode 1 is selected.
● D5, D6 are used for mode selection for group A (Upper Port C and Port A). The
format is as follows:
BSR mode format
üThis mode is selected by making

D7='0'.

ü D0 is used for bit set/reset. When D0= '1', the port C bit selected is SET, when D0
= '0', the port C bit is RESET.

ü D1, D2, D3 are used to select a particular port C bit .

8254 programmable interval timer

● 8254 is a device designed to solve the timing control problems in a

microprocessor
● It has 3 independent counters, each capable of handling clock inputs up to
10 MHz, and size of each counter is 16 bit.
● It operates in +5V regulated power supply and has 24 pin signals.
● Counting facility in both binary or BCD number system.
● Compatible with Intel and other microprocessor.
It includes a data bus buffer, read/write logic, control word register, and
counters.

1. Dats Bus Buffer:

● It is bidirectional 8 bit data bus buffer.
● It is used to interface 8254 data bus with system data bus.
● It is internally connected to internal data bus and its outer pins D0-
D7 are connected to system data bus.
● The direction of data buffer is decided by read and write control
signals.
The pin diagram for 8254 is :
Mode 0 (Interrupt on Terminal Count) –

● Mode 0 is typically used for counting.

● After the Control Word is written, OUT is initially low, and will remain low
until the counter reaches zero it is decremented by 1 after every clock
cycle.
● OUT then goes high and remains high until a new count or a new Mode 0
Control Word is written into the counter.
● GATE = 1 enables counting, GATE = 0 disables counting.
Mode 1 (programmable One Shot) –
● OUT will be initially high.
● OUT will go low on the CLK pulse following a trigger to begin the one-shot
pulse, and will remain low until the counter reaches zero.
Mode 2 (Rate Generator) –
● Initially value of OUT is low.
● When counting is enabled, it becomes high and this process repeats
periodically.
Mode 3 (Square Wave Generator) –

● Counting is enabled when GATE = 1 and disabled when GATE = 0.

● This mode is used to generate square waveform and time period (equal to count) is
generated.

Mode 4 (Software Triggered Strobe)

● In this mode counting is enabled by using GATE = 1 and disabled by GATE =

0.
● Initially value of OUT is high and becomes low when value of count is at last
Mode 5 (Hardware Triggered Strobe) –

● This mode generates a strobe in response to an externally generated signal.

● After it is initialized, the output goes high.
● When the terminal count is reached, the output goes low for one clock cycle.
8257 DMA Controller

● DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the

fastest rate.
● It allows the device to transfer the data directly to/from memory without any

interference of the CPU.

● Using a DMA controller, the device requests the CPU to hold its data, address and

control bus,
● so the device is free to transfer data directly to/from the memory.
● The DMA data transfer is initiated only after receiving HLDA signal from the CPU.
● The DMA controller chip 8257 works in two modes namely slave mode and
master mode.
● Likely the processor also works in two modes namely active mode and
HOLD mode.
● The processor normally works in active mode where the processor works as
the master of the computer system.
● The processor goes to the HOLD state only when DMA transfer is required
and it gives control to the system bus.
● When the processor is programming 8257 it is in slave mode.
● But at the time of reading the internal memory of the register it is in active
mode and becomes the master of the computer system.
● 8257 is used to control the DMA data transfer since it consists of four I/O ports.
● Every I/O port corresponds to a DMA channel.
● There is a DMA request called as DRQ input for every DMA channel, which
corresponds DMA acknowledge as output.
● Amidst each DMA channel consists of 16-bit address register and 16-bit count
register.
How DMA Operations are Performed?
● Initially, when any device has to send data between the device and the
memory, the device has to send DMA request (DRQ) to DMA
controller,which corresponds DMA acknowledge as output.
● The DMA controller sends Hold request (HRQ) to the CPU and waits
for the CPU to assert the HLDA.
● The CPU leaves the control over bus and acknowledges the HOLD
request through HLDA signal.
● Now the CPU is in HOLD state and the DMA controller has to manage
the operations over buses between the CPU, memory, and I/O devices.
Features of 8257
● It has four channels which can be used over four I/O devices.
● Each channel has 16-bit address and 14-bit counter.
● Each channel can transfer data up to 64kb.
● Each channel can be programmed independently.
● Each channel can perform read transfer, write transfer and verify transfer
operations.
● It operates in 2 modes, i.e., Master mode and Slave mode.
8257 Architecture
8257 Pin Description
DRQ0−DRQ3

● These are the four individual channel DMA request inputs, which are used by the
peripheral devices for using DMA services.
● When the fixed priority mode is selected, then DRQ0 has the highest priority and
DRQ3 has the lowest priority among them.
DACKo − DACK3

These are the active-low DMA acknowledge lines, which updates the requesting
peripheral about the status of their request by the CPU.
Do − D7

These are bidirectional, data lines which are used to interface the system bus with the
internal data bus of DMA controller.

In the Slave mode, it carries command words to 8257 and status word from 8257.

In the master mode, these lines are used to send higher byte of the generated address to the
latch. This address is further latched using ADSTB signal.
IOR

It is an active-low bidirectional input line, which is used by the CPU to read internal
registers of 8257 in the Slave mode.

In the master mode, it is used to read data from the peripheral devices during a memory
IOW

It is an active low bi-direction line, which is used to load the contents of the data bus to the
8-bit mode register of a 16-bit DMA address register. In the master mode, it is used to load
the data to the peripheral devices during DMA memory read cycle.
CLK

It is a clock frequency signal which is required for the internal operation of 8257.
RESET

This signal is used to RESET the DMA controller by disabling all the DMA channels.
Ao - A3

In the slave mode, they act as an input, which selects one of the registers to be read or
written. In the master mode, they are the four least significant memory address output
lines generated by 8257.
CS

It is an active-low chip select line. In the Slave mode, it enables the read/write
operations to/from 8257. In the master mode, it disables the read/write operations
to/from 8257.
A4 - A7

These are the higher nibble of the lower byte address generated by DMA in the master
READY

It is an active-high asynchronous input signal, which makes DMA ready by inserting wait
states.
HRQ

This signal is used to receive the hold request signal from the output device. In the slave
mode, it is connected with a DRQ input line 8257. In Master mode, it is connected with
HOLD input of the CPU.
HLDA

It is the hold acknowledgement signal which indicates the DMA controller that the bus has
been granted to the requesting peripheral by the CPU when it is set to 1.
MEMR

It is the low memory read signal, which is used to read the data from the addressed
memory locations during DMA read cycles.
MEMW

It is the active-low three state signal which is used to write the data to the addressed
memory location during DMA write operation.
ADST

This signal is used to convert the higher byte of the memory address generated by the
DMA controller into the latches.
AEN
TC

It stands for ‘Terminal Count’, which indicates the present DMA cycle to the presen
peripheral devices.

MARK

The mark will be activated after each 128 cycles or integral multiples of it from the
beginning. It indicates the current DMA cycle is the 128th cycle since the previous
MARK output to the selected peripheral device.
Vcc
Internal Registers of DMA Controller(university uq dec 2021)

1. Base Address Register (16 bit)

2. Base Word Count Register (16 bit)
3. Current Address Register (16 bit)
4. Current Word Count Register (16 bit)
5. Temporary Address Register (16 bit)
6. Temporary Word Count Register (16 bit)
7. Status Register (8 bit)
8. Command Register (8 bit)
9. Temporary Register (8 bit)
10. Mode Register (8 bit)
11. Mask Register (4 bit)
12. Request Register (4 bit)
Base Address Register:
It is a 16 bit register that stores the initial address from where the data
transfer will take place in a DMA Controller

Base Word Count Register:

It is a 16 bit register that stores the number of transfers to be performed

during an operation.
Current Address Register:

It is a 16 bit register that stores the memory address for DMA data
transfer.
Current Word Count Register:
It is a 16 bit register that stores the number of transfers remaining to be
performed during an operation.
1. Temporary Address Register:
It is a 16 bit register that stores the address of data during memory to
memory transfer in a DMA Controller.
2. Temporary Word Count Register:
It is a 16 bit register that stores the number of transfers to be performed
during a memory to memory transfer in a DMA Controller.
3. Status Register:
It is a 8 bit register that indicates which channel is currently under DMA
services or which channels has reached its terminal count.
1. Command Register:
It is a 8 bit register that programs the DMA operation and initializes the
channel to be used for data transfer.
2. Temporary Register:
It is a 8 bit register that holds data during memory to memory data
transfer.
3. Mode Register:
It is a 8 bit register that determines the operating mode, i.e., the transfer
mode and other transfer parameters, for a channel.
Mask Register:
It is a 4 bit register that is used to mask a channel from requesting the
DMA Services.

Request Register:
It is a 4 bit register that is used to request DMA data transfer by the
software.
dec2021