A Comprehensive Metrics

Driven Methodology to
Measure and Improve
Soft-IP Quality
Anuj Kumar - Atrenta
Andy Wu - TSMC

This presentation may contain forward-looking statements regarding product development. Information or statements contained in this presentation are for informational
purposes only and do not represent a commitment, promise, or legal obligation of any kind by Atrenta Inc. or its affiliates.

DAC 2014 - IP Track Submission

Background and Motivation

Standardize IP Handoff & Acceptance Quality Checks

 To define a comprehensive set of quality checks to assess the implementation readiness
for soft IPs to enable a smooth IP handoff / acceptance flow.
 These quality checks are derived from Atrenta’s Reference GuideWare 2.0 Methodology
for IP and SoC RTL Signoff and later renamed as “TSMC Soft IP Quality Golden Rules”
 TSMC Soft IP Quality Checks should be equally applicable for different types of Soft IP
e.g. internal, legacy, or 3rd party RTL IPs / Blocks
Enable Easy Adoption of the Flow to Benefit a Wide Variety of IP-SoC Ecosystem
Partners
 The IP Qualification flow should be easy to setup
 Get to the meaningful (high coverage low noise) results with self guided and systematic
approach
Provide Portable, Easy to Read / Correlate, and Quality Metrics Objective-based
Handoff / Acceptance Reports
Flow Should be Scalable and Easy to Integrate in Existing Design Flow
Environments

DAC 2014 - IP Track Submission 2

Overview of TSMC 9000 Soft IP Qualification Program

IP Ecosystem TSMC End Customers

Partners Online
IP supplier 1 Atrenta IP1 Chip project 1
DashBoard
IP 2
IP supplier 2 Chip project 2
TSMC IP TSMC IP
Kit Kit
IP 3
IP supplier 3 Chip project 3
Handoff
… IP n Inspection /
Atrenta Acceptance …
IP supplier n DataSheet
Chip project n

DAC 2014 - IP Track Submission 3

TSMC IP IP
TSMC Handoff KitKit
Handoff
IP

TSMC IP Handoff Kit

GuideWare goals Doc, training, scripts

Physical
Constr
Power
CDC

Quickstart Training Scripts,

DFT
Lint

Guide module setup

IP Design Intent IP reports

waivers
FSDB,…
UPF/CPF

Deliverables
SGDC
RTL

…. Atrenta Atrenta
SDC

DataSheet DashBoard

SpyGlass Clean
IP
DAC 2014 - IP Track Submission 4
TSMC IP Handoff Kit – Inputs / Outputs

TSMC IP Handoff Kit

Project file
TSMC IP Handoff Std. Design
Tech Libs Methodology
SGDC file Constraints
(.lib) Simulation Inputs
SpyGlass Waiver file (SDC, VCD/FSDB,
UPF/CPF)
Other setup
RTL files
(.v/.sv/.vhd)

IP Handoff Deliverables
RTL+TechLibs Design Analysis/Quality Metrics Reports SpyGlass Setup Files
RTL CDC DataSheet moresimple SpyGlass SDC
Tech Libs Fault Covg DashBoard count Project File UPF/CPF
(.prj)
Waivers
Power Sign_off
(.swl)
SGDC VCD/FSDB/SAIF
SDC
Coverage

DAC 2014 - IP Track Submission 5

Key Soft IP-Kit Quality Checks
 Best practices lint checks IP
 IP readiness for simulation & synthesis analysis
TSMC IP Kit
 Identification of deadcode, x-assignment, unreachable states SG-Lint
 Multi mode/corner/design scenarios RTL Power Estimation SG-AdvanceLint
 Power Intent(UPF/CPF) verification SG-Power
 Fault/Test Coverage Analysis (Stuck@ & Transition) SG-PowerVerify
 Clock/Reset Propagation (Glitch, convergence) Analysis SG-DFT
 Asynchronous Clock Domain Crossing Path Verification SG-Clocks
 Timing constraints(SDC) checks for completeness & consistency SG-Constraints
 Verification of Timing Exceptions(FP,MCP) SG-Txv
 Area, timing(negative slack paths) & congestion analysis SG-Physical

SpyGlass Clean
IP

DAC 2014 - IP Track Submission 6

TSMC IP Kit Execution Flow
 Auto-generation of SpyGlass setup files
Design Read (.prj, .sgdc, .swl, .dat ,etc.)
>% aipk_read -top foo –srcfile foo.f –libfile lib.f –sdcfile foo.sdc  Generation of Design Read DashBoard report
-activity_file foo.vcd  Ensures that RTL is read in successfully

 Identifies unconstrained clock/resets in the

Design Setup Checks design
 Ensures that design setup is complete &
>% aipk_read –top foo
correct

Basic Design Checks  Runs basic IP handoff checks (Lint, CDC-

Structural, DFT, SDC, Power)
>% aipk_run –top foo –goals basic_check  Generates quality report for basic design
checks/goals

 Runs advanced IP handoff checks (CDC

Advanced Design Checks functional, Lint functional & physical)
>% aipk_run –top foo –goals adv_check  Generates overall quality report combining
results for basic & advanced checks

 Packages an IP with design intent, setup &

IP Packaging analysis reports
>% aipk_pack –top foo –save_all

DAC 2014 - IP Track Submission 7

Soft IP Quality Metrics DashBoard Report

DAC 2014 - IP Track Submission 8

IP Specification/Datasheet Report
TSMC IP Kit generates the SpyGlass DataSheet report capturing key design specifications
and profile statistics, once all goals run are finished

Design IP
Design Design
Setup
Read Analysis Packaging
Check

DAC 2014 - IP Track Submission 9

Sample Results from TSMC IP Kit Analysis
IPStats CDC Test SDC Power

Gate Count

Instance Count

Flop Count

Unsynchronized CDCs

Synchronized CDCs

Test Coverage(stuck@)

Test Coverage(transition@)

% ports constrained

% registers constrained

No. of unverified FP
No. of unverified MCP

Internal (mW)

Leakage (uW)

Switching (mW)
Core-1 21885 8817 462 130 22 98 94.3 98 100 0 0 4 72.9 2.3
Vendor A 8668514 2154640 46637 36 212 88 85.3 65 100 0 0 65 350 79
Vendor B 639021 227585 8907 22027 40626 99 92.3 81 100 0 0 23 2880 15
Vendor C -IP1 57000 23000 2537 275 757 100 98.7 98 100 2 0 11 13.9 4.9
Vendor C-IP2 95000 39000 9000 4279 1387 100 91.2 89 99 0 0 40 21.7 65
Vendor C-IP3 110000 47000 4806 2552 3802 99 94.1 99 100 0 0 12 24.2 12
Vendor D-IP1 2201603 489245 94023 12 47 98 91.8 99 100 0 2 118 1870 115
Vendor D-IP2 907303 210201 59125 121 65 99 91 100 100 0 0 117 8140 20
Vendor E-IP1 70439 20125 4546 1300 523 99.7 94.9 100 100 0 8 9.46 64.2 0.95
…

30+ Soft IPs qualified from 20 different IP vendors enrolled in

the TSMC Soft IP 9000 Program so far….
DAC 2014 - IP Track Submission 10
TSMC IP Kit – A Typical User Adoption Flow
IP1 IP1 IP1
IP1
Legacy IP1
New IP1
3rd party IP
IP RTL blocks IP Suppliers

TSMC IP
STANDARDIZED IP INSPECTION Kit

Atrenta DataSheet
IP1 IP1 IP1 Atrenta DashBoard
IP1 IP1 RTL IP1
Legacy New
3rd party IP +
IP blocks blocks IP design intent

HIGH QUALITY IP

BLK 1
BLK 2
SoC Integrators
BLK3
BLK n

SoC MINIMIZE ITERATIONS

SMOOTH SoC INTEGRATION
DAC 2014 - IP Track Submission 11
TSMC IP Kit – User Benefits
Standardized inspection flow for all
IPs including ones from internal
sources (new, legacy, older designs)
 Maximize internal IP re-use
Propagate IP design intent – Beyond functional verification…
SDC/SGDC, waivers, *PF, … for Verify IP for CDC, SDC, DFT,
chip integration *PF, …
 IP integrates efficiently  Fully verified IP

Automated regression flow runs

Review DataSheet and DashBoard to Create an IP repository with
the IP kit nightly and generates
select the correct IP published reports
DataSheet & DashBoard reports
 IP selection based on  Streamline IP delivery
 Automatically track IP
objective quality & spec metrics and track usage
updates/ bug fixes

DAC 2014 - IP Track Submission 12

Summary / Conclusion
SpyGlass, TSMC Soft IP Quality Golden/GuideWare Rules and Atrenta
Design analysis reports(DashBoard/DataSheet) together provide
a comprehensive, detailed and design objective
based Soft-IP quality assessment report.
TSMC and Atrenta have partnered to adapt these tools for TSMC’s soft IP
9000 Qualification Program.
A comprehensive set of quality checks, as included in TSMC IP Kit, has
been defined and documented in Design Metric Reports.
TSMC IP Kit Flow successfully adopted by 20+ IP ecosystem partners,
which was quite helpful in improving the implementation readiness for
their various Soft-IPs.
Summary results of IPs for IP ecosystem partners are posted on TSMC
Online

DAC 2014 - IP Track Submission 13