503528-3 – Digital System Design

State Machine Charts using

VHDL

(Lecture #3)

Rashid A Saeed

Fall 2021@Rashid A Saeed 1

Course Content
Course Learning Outcomes
 Outline

1. VHDL for Combinational Circuits

2. VHDL for Sequential Circuits

Fall 2021@Rashid A Saeed 503528 Digital Systems Design 4

 Overview

• Basic storage elements

–Structural design using library components
–Behavioral design: D latches and D flip-flops
• Options including
–Synchronous and asynchronous reset
–Multiplexed inputs
–Enable inputs

• Counters
• Shift Registers
• Arbitrary finite state machines (FSM)
–Mealy and Moore model designs

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 Agenda

Half Adder
Full Adder
Lookahead carry
Subtraction
Dual Mode M=0 (adder), M=1 (Subtracter)
Overflow
Comparator
Decoder
Encoder (4- Bit Priority, Decimal to Binary or BCD
Encoder) 6

Mux & DeMux

 Latch
 SR latch
 D Latch
 D FF
 JK FF
 T FF
 Counters
 Registers
7
 Modeling Flip-Flops Using VHDL Processes
VHDL Code for a
Simple D Flip-Flop

VHDL Code for a

Transparent Latch
 Modeling Flip-Flops Using VHDL Processes
VHDL Code For a D
Flip-flop with
Asynchronous Clear

process(sensitivity-list)
A basic process form: Begin
sequential-statements
end process;
 Modeling Flip-Flops Using VHDL Processes
1 entity JKFF is
J-K Flip-Flop 2 Port (SN, RN, J, K, CLK: in bit; Q, QN: out bit);
Model 3 end JKFF;
4 architecture JKFF1 of JKFF is
5 signal Qint: bit; --- internal value of Q
6 begin
7 Q<=Qint;
8 QN<=not Qint;
9 process (SN, RN, CLK)
10 begin
11 if RN=‘0’ then Qint<=‘0’ after 8ns; --- RN=‘0’ will clear the FF
12 elsif SN=‘0’ then Qint<=‘1’ after 8ns; --- SN=‘0’ will set the FF
13 elsif CLK’event and CLK =‘0’ then --- falling edge of CLK
14 Qint<=(J and not Qint) or (not K and Qint) after 10ns;
15 end if;
16 end process;
17 end JKFF1;
 Modeling Registers and Counters Using VHDL Processes

Cyclic Shift Register

Sequential statements without delay

Q1  Q3; Q 2  Q1; Q3  Q 2;
 Modeling Registers and Counters Using VHDL Processes
Register with
Synchronous
Clear and Load

Left-Shift Register
with Synchronous
Clear and Load
 Modeling Registers and Counters Using VHDL Processes

VHDL Code for a Simple Synchronous Counter

 1. VHDL for FSM Sequential Circuits

Fall 2021@Rashid A Saeed 503528 Digital Systems Design 14

 Overview

• Basic storage elements

–Structural design using library components
–Behavioral design: D latches and D flip-flops
• Options including
–Synchronous and asynchronous reset
–Multiplexed inputs
–Enable inputs

• Counters
• Shift Registers
• Arbitrary finite state machines (FSM)
–Mealy and Moore model designs

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 Arbitrary FSM design using
CAD tools
• VHDL provides a number of constructs for designing
finite state machines
• There is no a standard way for defining an FSM
• Basic approach
 Create a user-defined data type to represent the
possible states of an FSM
 This signal represents the outputs (state variables)
of the flip-flops that implement the states in the FSM
 VHDL compiler chooses the appropriate number of
flip-flops during the synthesis process
 The state assignment can be done by the compiler
or can be user specified
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 User defined data types

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 Representing states

• A SIGNAL is defined, of the user-defined fsm_state, to

represent the flip-flop outputs

type fsm_state is (a, b, c);

signal y: fsm_state;

The signal, y, can be used to represent the flip-flop

outputs for an FSM that has three states

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 Design example using Moore SM
Example

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 VHDL design example

library ieee;
use ieee.std_logic_1164.all;

entity detect is
port( clk, reset_n, w : in std_logic;
z : out std_logic);
end detect;

architecture behavior of detect is

type fsm_state is (a,b,c);
signal y: fsm_state;
begin

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process (reset_n, clk)
begin when c =>
if reset_n = ‘0’ then y if w=‘0’ then
<= a; y <= a;
elsif rising_edge(clk)
then case y is
else
when a => y <= c;
if w=‘0’ then end if;
y <= a; end case;
else end if;
y <= b; end if;
when b =>
end process;
if w=‘0’ then z <= ‘1’ when y=c
y <= a; else ‘0’;
else end behavior;
y <= c; end if;

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 VHDL code of a Mealy FSM

 A Mealy FSM can be described in a similar manner as a

Moore FSM
 The state transitions are described in the same way as
the original VHDL example
 The major difference in the case of a Mealy FSM is the
way in which the code for the output is written
 Recall the Mealy state diagram for the ’11’ sequence
detector
reset

1/0

A B 1/1
w/z 0/0
0/0
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Mealy ’11’ detector VHDL
code

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 https://www.allaboutcircuits.com/
textbook/digital/chpt-11/finite-state-
machines/

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