Course Name- Microprocessor

Course Code- COM-503

Topic – Branch Penalties in RISC Architecture

Model Institute of
Engineering & Technology
 Introduction

 Branch penalties refer to the performance impact that occurs when a

processor encounters a branch instruction in a program.
 A branch instruction is a command that alters the normal sequential flow of
instructions by directing the program to jump to a different part of the code
based on a condition (such as an if statement or a loop).
 Branch penalties arise due to the delay caused by fetching and executing
the correct instructions after a branch is encountered.

 When a branch instruction is encountered, the processor needs to determine

the outcome of the branch (i.e., whether it will be taken or not taken)
before proceeding with the execution of subsequent instructions.

 This determination of the branch outcome introduces delays in the

instruction pipeline of the processor, impacting its performance.
 The penalties associated with branches include:
 Pipeline Stalls: Fetching and executing the correct instructions following a
branch can cause a delay in the pipeline, leading to stalls where the
processor is idle until the correct instructions are fetched.

 Instruction Fetch Delays: When a branch is encountered, the processor

needs to fetch the instructions from the correct target address. If the branch
outcome is not yet known, the processor may have to wait until the outcome
is resolved, leading to delays in fetching subsequent instructions.

 Mispredictions: In cases where branch prediction techniques are used and

the prediction is incorrect, the processor may have already executed
instructions based on the wrong prediction. When the correct branch
outcome is determined later, the incorrectly executed instructions may need
to be discarded or rolled back, causing inefficiencies.
 Reducing branch penalties is crucial for optimizing processor
performance.

 Techniques such as branch prediction, branch target buffers, delayed

branching, and speculative execution are used in modern processors
to mitigate the impact of branch penalties and keep the processor
pipeline filled with the correct instructions for efficient execution.
 Reducing branch penalties in a Reduced Instruction Set Computing
(RISC) architecture involves employing various techniques to
mitigate the performance impact of branch instructions. Branch
penalties occur when a processor encounters a branch instruction that
changes the flow of program execution, leading to a delay while
waiting for the correct instructions to be fetched and executed.
 Here are some approaches used in RISC architectures to reduce

branch penalties:
 Branch Prediction: Predicting the outcome of branches before their

actual resolution helps in fetching and executing the correct

instructions. Techniques like static prediction, where branches are
predicted based on statistical information, or dynamic prediction,
which uses algorithms and history to predict branches, are used to
minimize delays.
 Branch Target Buffer (BTB): BTB caches branch target addresses,
helping processors to quickly retrieve the target instruction when a
branch is resolved, reducing fetch delays.

 Delayed Branches: Some RISC architectures use delayed branching,

where the instruction following a branch is executed regardless of the
branch outcome. This helps in keeping the pipeline filled and reduces
the impact of branch penalties.

 Hardware Interlocking and Pipelining: Employing techniques to

optimize the pipeline for branch instructions can reduce penalties. For
instance, utilizing hardware interlocking to allow other instructions to
execute while waiting for the branch outcome.
 Compiler Optimizations: Advanced compilers can optimize code to minimize the
impact of branches. Techniques like loop unrolling, software pipelining, and
predication help in reducing the number of branches or making them predictable,
hence reducing penalties.
 Speculative Execution: In more advanced processors, speculative execution is
used where the processor speculatively executes instructions along the predicted
branch path. If the prediction is correct, it helps to avoid the delay caused by
waiting for the actual branch outcome.
 Branch Not Taken Approach: Some RISC architectures use the 'branch not taken'
approach by organizing code to assume that branches are not taken, reducing the
penalties for such scenarios.

 Reducing branch penalties is crucial in enhancing the performance of RISC

architectures, as branches are an inherent part of program execution. Employing a
combination of these techniques helps processors to minimize the performance
impact caused by branches and maintain efficient program execution.
 Branch Prediction in RISC

 In Reduced Instruction Set Computing (RISC) architectures, branch prediction

plays a crucial role in optimizing performance due to the emphasis on simple and
efficient instructions. RISC architectures typically prioritize executing instructions
in a pipelined and efficient manner, making branch prediction strategies significant
for maintaining instruction throughput and minimizing delays caused by branching
instructions.
 Here are some common branch prediction approaches used in RISC architectures:
 Static Prediction: RISC architectures might employ simple static prediction
strategies, such as assuming that certain types of branches (e.g., backward branches
in loops) are taken or not taken based on typical programming patterns. This
method doesn't rely on dynamic runtime information but rather on fixed rules.

 Branch Target Buffer (BTB): Many RISC architectures utilize a BTB, which
caches branch target addresses along with predictions of whether the branch will be
taken or not. The BTB helps in quickly fetching the correct instructions when a
branch is encountered again.
 Delayed Branches: Some RISC designs include delayed branching, where instructions
following the branch are executed before the branch decision is confirmed. This helps in
maintaining the pipeline filled and reduces the impact of branch penalties.
 Compiler Techniques: Advanced compilers for RISC architectures might optimize code
to minimize the need for branches or make them more predictable. Techniques like loop
unrolling, software pipelining, and optimizing branch instructions can enhance
predictability.
 Instruction Prefetching: Strategies involving instruction prefetching aim to fetch
instructions ahead of time, anticipating the likely execution path based on branch
predictions. This helps in reducing stalls due to fetching instructions after a branch.
 Hardware Predictors: Some RISC processors use sophisticated hardware predictors,
including dynamic predictors like two-level adaptive predictors or tournament predictors,
to more accurately predict branches based on runtime behavior and patterns.
 RISC architectures focus on efficient execution, and these branch prediction techniques
are geared towards minimizing the impact of branching instructions on the pipeline and
overall performance. Combining different prediction methods helps RISC processors
execute code more swiftly and with minimal stalls caused by branch instructions.