ARM

PROCESSO
R
PRESENTED BY: ANUSHREE GOSWAMI
 RISC

• RISC stands for Reduced Instruction Set Computer.

• designed to process limited computer instructions to operate at a much higher speed.
• Separate digital circuitry
• Examples:
 IBM RS6000, MC88100
 DEC’s Alpha 21064, 21164 and 21264 processors
 FEATURES OF RISC
RISC processors use a
small and limited
number of instructions.
Instruction is of
Delayed
uniform fixed
branch.
length.

Simple
Pipelining addressing
modes.

hardwired Large Number

control unit of Registers.
 ARM

• ARM - Advanced RISC Machine

• 32-bit RISC microcontroller
• used in portable devices, wireless communication technologies and other embedded systems
• This needs very few instruction sets and transistors
• less power consumption
 FEATURES OF ARM
Load/store
architecture.

An orthogonal
Link registers
instruction set.

Hardware Mostly single-

virtualization s cycle
upport. execution.

64 and 32-bit execution Enhanced

states for scalable high power-saving
performance. design.
How is ARM different
from pure RISC
• Variable cycle execution for
certain instructions
• Inline barrel shifter leading to
more complex instructions
• Thumb 16-bit instruction set
• Conditional execution
• Enhanced instructions
CLASSIFICATIO
N
 ARMxyzTDMIEJFS

x series T Thumb I EmbeddedICE

F Jazelle

Enhanced
y MMU
D Debugger E instruction S Floating-point

Synthesizible
z cache M Multiplier
J version
 CORE
ARCHITECTURE
 CORE
ARCHITECTURE
Data bus • Data enters the ARM core through the Data Bus

Barrel Shifter • Register contents pre-processed before applying to ALU

• upgrades the address register before the core reads the

Incrementor next

Register file • storing data

• storing the address

Address register
• instructions that require signed values, convert 8/16 bit to 32
Sign extend bit

Instruction decoder • decodes the instructions

 ARM CORTEX-M3

• Cortex-M3 processor is a high performance low-cost 32-

bit processor.
• Harvard Architecture
• 3-stage pipeline to fetch, decode, and execute
• cost-sensitive device
• implemented by the THUMB instruction sets based
on THUMB-2 technology.
ARM CORTEX-M3
PROGRAMMERS
MODEL
7 modes of operation Privileged: FIQ, IRQ, Supervisor, Abort, Undefined,
User System
Non-privileged: User
FIQ
IRQ
Supervisor 37 registers of 32-bit
• 30 general purpose registers
Abort
• 1 dedicated program counter (pc)
Undefined • 1 dedicated current program status register (cpsr)
System • 5 dedicated saved program status registers (spsr)
 REGISTER
ORGANISATION
 PROGRAM STATUS REGISTERS
1) Current Processor Status Register (CPSR)
2) Save Program Status Register (SPSR)
EXCEPTIONS/INTERRUPTS
EXCEPTIONS/INTERRUPTS

Reset - executed on power on

Undef - when an invalid instruction reaches the execute stage of the
pipeline
SWI - when a software interrupt instruction is executed
Prefetch - when an instruction is fetched from memory that is
invalid for some reason, if it reaches the execute stage then this
exception is taken
Dataa - if a load/store instruction tries to access an invalid memory
location, then this exception is taken
IRQ - normal interrupt
FIQ - fast interrupt
EXCEPTION / INTERRUPT handling
When an exception occurs, the ARM:
Copies CPSR into SPSR_<mode>
Sets appropriate CPSR bits
Change to ARM state
Change to exception mode
Disable interrupts (if appropriate)
Stores the return address in LR_<mode>
Sets PC to vector address

To return, exception handler needs to:

Restore CPSR from SPSR_<mode>
Restore PC from LR_<mode>
 ADDRESSING
MODES
Addressing mode refers to different methods of selecting the operand.
 Addressing modes for data processing
operands
Unmodified value

Modified value
Logical shift left
Logical shift right
Arithmetic shift right
Rotate right
Rotate right extended
 Addressing modes for data processing
operands
Register indirect addressing mode

Relative register indirect addressing mode

Base indexed indirect addressing mode

Base with scale register addressing mode

INSTRUCTION
SET
• Control Flow instructions
• Data Processing Instructions
• Multiply Instructions.
• Data transfer Instructions
• Program Status Register Access Instructions.
• Swap Instructions.
• Counting Leading Zeros Instruction
• Exception/Software Interrupt generating Instructions.
• Multiple Register Transfer Instructions.
• Co-processor Instructions.
ADVANTAGES AND DISADVANTAGES
ADVANTAGES
• Affordable to create
• Low Power Consumption
• Work more quickly
• Feature of multiprocessing
• Improved Battery Life
DISADVANTAGES
• scheduling instructions are
problematic
• Programmers with a high level
of expertise are required
• scheduling instructions are
problematic
• incompatible with X86
THANKS
!
Does anyone have any questions?

PRESENTED
CREDITS: BY: ANUSHREE
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