This document discusses approaches to minimize leakage power in integrated circuits. It covers why leakage power has become an issue with scaling, how threshold voltage scaling affects leakage, and techniques for fabricating multiple threshold voltages including multiple channel doping, oxide thickness, channel length, and body bias. It also summarizes approaches for leakage reduction including transistor stacking, VTCMOS, and MTCMOS. Simulation results are presented and advantages/limitations of MTCMOS are discussed. References for further reading on the topic are provided.
This document discusses approaches to minimize leakage power in integrated circuits. It covers why leakage power has become an issue with scaling, how threshold voltage scaling affects leakage, and techniques for fabricating multiple threshold voltages including multiple channel doping, oxide thickness, channel length, and body bias. It also summarizes approaches for leakage reduction including transistor stacking, VTCMOS, and MTCMOS. Simulation results are presented and advantages/limitations of MTCMOS are discussed. References for further reading on the topic are provided.
This document discusses approaches to minimize leakage power in integrated circuits. It covers why leakage power has become an issue with scaling, how threshold voltage scaling affects leakage, and techniques for fabricating multiple threshold voltages including multiple channel doping, oxide thickness, channel length, and body bias. It also summarizes approaches for leakage reduction including transistor stacking, VTCMOS, and MTCMOS. Simulation results are presented and advantages/limitations of MTCMOS are discussed. References for further reading on the topic are provided.