Vector Processing Unit

Integrated RISC-V
Processor
Group Members: Supervisors:
Muhammad Nadeem Dr. Sajid Gul Khawaja
Co-Supervisor
Dr. Muhammad Yaseen
Ahsan Ali
Yaseen
Shahzad Akhter
 https://github.com/ucerd/Summer-School-2023_2/blob/main/3.%20RISC-V-processor-based-chip-IP-design-%20AQ
L%20Tech.pdf

https://www.hpcwire.com/2023/07/19/how-china-is-building-an-open-national-chip-
plan-around-risc-v/#:~:text=The%20RISC%2DV%20ecosystem%20in,design%20automa
tion%2C%20and%20verification%20tools.

https://www.theregister.com/2023/10/04/samsung_cozies_up_to_riscv/

https://www.embedded.com/dac-2023-risc-v-is-not-in-the-future-its-n
ow/#:~:text=A%20key%20message%20from%20the,and%20it's%20a%2
0reality%20now.%E2%80%9D

https://www.eenewseurope.com/en/meta-details-its-first-custom-risc-v-ai-silicon/
RISC-V Market Growth

Semiconductor processor IP market roughly $4 Billion a year Strong RISC-V IP & SW growth
OBJECTIVES

Design and
Understanding Simulation of implementation
of RISC-V RISC-V of FPGA-
supported VPU

Integration of Execution on Analysis of Final

VPU with RISC-V FPGA Core
 WHAT’S ALREADY DONE?

https://www.design-reuse.com/news/54142/semidynamics-vector-unit-64-bit-risc-v-cores.html#:~:text=Semidynamics%20supports%20DLEN%20configurations%20from,%2C%2032
%2Dvector%20core%20option.
 CONT…

https://riscv.org/blog/2022/06/risc-v-vector-processing-is-taking-off-sifive http://www.andestech.com/en/2022/12/08/andes-announces-risc-v-multicore-1024-bit-vector
-processor-ax45mpv/
 Instruction
Name Description Version Status
Extensions Count
Standard Extension for Integer
M 2.0 Frozen 8
Multiplication and Division
Standard Extension for Single-Precision
F 2.0 Frozen 25
Floating-Point
Standard Extension for Double-Precision
D 2.0 Frozen 25
Floating-Point
Standard Extension for Quad-Precision
Q 2.0 Frozen 27
Floating-Point
Standard Extension for Decimal Floating-
L 0.0 Open Undefined Yet
Point
Standard Extension for Compressed
C 2.0 Frozen 36
Instructions

B Standard Extension for Bit Manipulation 0.90 Open 42

Standard Extension for Packed-SIMD

P 0.1 Open Undefined Yet
Instructions

V Standard Extension for Vector Operations 0.7 Open 186

 Program
Memory
SYSTEM UART

LEVEL
DIAGRAM NICE
Interface
 Intended Methodology & Work Done So Far
Understanding of RISC-V
• Base ISA of RISC-V
• Research & Comparison of RISC-V Cores
• Selected core: HummingBirdv2 E203
https://github.com/riscv-mcu/e203_hbirdv2

Understanding and Implementation of VPU

• Base Paper(s) for VPU Design

Cavalcante, M., Schuiki, F., Zaruba, F., Schaffner, M. and
Benini, L., 2019. Ara: A 1-GHz+ scalable and energy-efficient
RISC-V vector processor with multiprecision floating-point
support in 22-nm FD-SOI. IEEE Transactions on Very Large
Scale Integration (VLSI) Systems, 28(2), pp.530-543.
Perotti, M., Cavalcante, M., Wistoff, N., Andri, R., Cavigelli, L.
and Benini, L., 2022, July. A “new ara” for vector computing:
An open source highly efficient risc-v v 1.0 vector processor
design. In 2022 IEEE 33rd International Conference on
Application-specific Systems, Architectures and Processors
(ASAP) (pp. 43-51). IEEE.
 Single Lane

VPU
 HummingBirdv2 E203
Integration of VPU with scalar Main RISC-V Core
core
• Nuclei Instruction Co-unit Extension
(NICE) Interface NICE Interface
Request Channel Response Channel Memory Request Channel Memory Response Channel

valid
ready
valid

err
rs1
rs2
instr

rdata
ready
FPGA Implementation

holdup

wdata
ready

ready
valid
valid

addr
read
size
data
• Implementation of VPU enabled RISC-

err
V core on FPGA (ZYNQ)

Designed VPU
Cross-Compilation Toolchain Setup-Linux

Components:
• RISC-V GNU Compiler Toolchain
• Spike (RISC-V ISA Simulator)
• Proxy Kernel (pk)
• Low-Level Virtual Machine (LLVM)
https://github.com/riscv-collab/riscv-gnu-toolchain
Steps:
• Clone the toolchain directory into the
local machine
• Configure Environment Variables
• Build and Install the RISC-V Toolchain
• Install and Configure Spike and pk
• Vector instruction’s support using LLVM

Results:
• Successful compilation of sample program
Contd.
RISC-V GNU Compilation Toolchain:
• GCC compiler
• Binutils (linker ,assembler etc.)
• Libraries

Spike: RISC-V ISA Simulator

• Support for all extensions of RISC-V
• Multiple CPU support "D:\FYP\TOOLCHAIN\output32.dis"

Proxy Kernel (PK)

• Software bridge for RISC-V
processor
• Memory management and
basic I/O
"D:\FYP\TOOLCHAIN\convolution32.dis"
DFT Code Execution with RISC-V Toolchain
DFT C Code

Disassembly of
C Code

Console Output
Analysis of the final core
• Comparison of the integrated core with scalar
• Number of lines of assembly code
• Latency
• Number of cycles (CPI)

Addition Code DFT Code

Technology

QuestaSIM Vivado

Cross- FPGA Board

RISC-V
compilation Tools (ZYNQ)
DELIVERABLES AND KPIs

Deliverables KPIs
• Open-source VPU based on • Real-Time Execution of
HDL Verilog Integrated RISC-V core on FPGA
• VPU Integrated RISC-V code
• Cross-compilation toolchain for
testing and simulation
 TEAM 01 TEAM 02
WORK DIVISION Muhammad Nadeem
Muhammad Haris
Ahsan Ali
Shahzad Akhter

STEP 01 STEP 02 STEP 03 STEP 04 STEP 05

In-depth Implementatio
Understanding
Understanding n of VPU
of Verilog Research on BOTH TEAMS
of RISC-V and Integrated
RISC-V Cores Design of VPU RISC-V on
Core(Code-
Reviewing & Integration FPGA
wise)
Concepts of CSA of VPU with
main RISC-V
BOTH TEAMS Simulation of Core Analysis/
Cross-
Implementation compilation selected RISC-V Benchmarking
of Basic Custom Toolchain Setup Core of Core
Processor
 TIMELINE (tentative)

Jul Sep-Oct Jan-Feb-Mar

Research on RISC-V Design and Implementation of VPU
platforms/cores & Cross- implementation of FPGA- integrated RISC-V core on
compilation toolchain supported VPU FPGA & Analysis of Core
setup

In-depth Integration of VPU

Understanding of
understanding of with RISC-V
Verilog & Reviewing
RISC-V core(code-
concepts of CSA Jul-Aug Oct-Nov-Dec Apr-May
wise) & Simulation
of selected RISC-V
core
THANK YOU
Simulation of Core
• Verilog Testbench
• Examples