1

REVISION ON DIGITAL ELECTRONICS I

PART 2
 2 Introduction

DIGITAL LOGIC CIRCUITS

 Logic Gates
 Boolean Algebra
 Map Simplification
 Combinational Circuits
 Flip-Flops
 Sequential Circuits
 3 Logic Gates

BASIC LOGIC BLOCK - GATE -

Binary Binary
Digital Digital
. Gate Output
Input .
Signal . Signal

Types of Basic Logic Blocks

- Combinational Logic Block

Logic Blocks which is the output logic value
depends only on the input logic value

- Sequential Logic Block

Logic Blocks which is output logic value
depends on the input value and the
state (stored information) of the blocks

Functions of Gates can be described by

- Truth Table
- Boolean Function
- Karnaugh Map
 4 Logic Gates

COMBINATIONAL GATES
Name Symbol Function Truth Table
A B X
A X=A•B 0 0 0
AND B
X or
X = AB
0
1
1
0
0
0
1 1 1
A B X
A 0 0 0
OR X X=A+B 0 1 1
B 1 0 1
1 1 1
A X
NOT A X X=A 0
1
1
0
A X
Buffer A X X=A 0
1
0
1
A B X
A 0 0 1
NAND X X = (AB) 0
1
1
0
1
1
B 1 1 0
A B X
A 0 0 1
NOR X X= A+B 0 1 0
B 1 0 0
1 1 0
A X=AB A B X
XOR X or 0 0 0
Exclusive OR 0 1 1
B X = A B + AB 1 0 1
1 1 0
A B X
A X= AB
XNOR X or
0
0
0
1
1
0
Exclusive NOR
or Equivalence B X = A B + AB 1 0 0
1 1 1
 5 Boolean Algebra

BOOLEAN ALGEBRA
Boolean Algebra

 Boolean Algebra is useful in analysis and synthesis of digital logic

circuits
-Input and Output signals can be represented by Boolean
Variables
-Function of the digital logic circuits can be represented by Logic
Operations, i.e., Boolean Expression(s)
-From a Boolean function, a logic diagram can be constructed
using AND, OR, and NOT.
-Standard forms of Boolean Expressions:
f ( A, B, C )  ABC  ABC  ABC
1. Sum-of-Product (SOP)
• All variables appear in each product term.
• Each of the product term in the expression is called as
minterm.
f ( A, B, C )  ( A  B  C )  ( A  B  C )  ( A  B  C )
2. Product-of-Sum (POS)
• All variables appear in each product term.
• Each of the product term in the expression is called as
maxterm.
 6 Boolean Algebra

LOGIC CIRCUIT DESIGN

x y z F
0 0 0 0
0 0 1 1
Truth 0 1 0 0
Table 0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

Boolean
Function F = x + yz

x
Logic F
y
Diagram
z
 7 Boolean Algebra

BASIC IDENTITIES OF BOOLEAN ALGEBRA

[1] x + 0 = x [2] x • 0 = 0
[3] x + 1 = 1 [4] x • 1 = x
[5] x + x = x [6] x • x = x
[7] x + x = 1 [8] x • X = 0
[9] x + y = y + x [10] xy = yx
[11] x + (y + z) = (x + y) + z [12] x(yz) = (xy)z
[13] x(y + z) = xy +xz [14] x + yz = (x + y)(x + z)
[15] (x + y) = xy [16] (xy) = x + y [15] and [16] :
De Morgan’s Theorem
[17] (x) = x
Usefulness of this Table
- Simplification of the Boolean function
- Derivation of equivalent Boolean functions to obtain logic diagrams
utilizing different logic gates
• Ordinarily ANDs, ORs, and Inverters
• But a certain different form of Boolean function may be
convenient to obtain circuits with NANDs or NORs
→ Applications of De Morgans Theorem
x.y = (x + y) x + y= (xy)
NOT, AND → NOR NOT, OR → NAND
 8 Map Simplification

SIMPLIFICATION

Truth Boolean
Table Function
Unique Many different expressions exist
Simplification from Boolean function

- Finding an equivalent expression that is least expensive to implement

- For a simple function, it is possible to obtain a simple expression for
low cost implementation
- But, with complex functions, it is a very difficult task

Karnaugh Map (K-map) is a simple procedure for simplifying Boolean

expressions.

Truth
Table
Simplified
Karnaugh Boolean
Map Function
Boolean
function
 9 Map Simplification

KARNAUGH MAP
Karnaugh Map for an n-input digital logic circuit (n-variable sum-of-products
form of Boolean Function, or Truth Table) is
- Rectangle divided into 2n cells
- Each cell is associated with a Minterm
- An output(function) value for each input value associated with a
mintern is written in the cell representing the minterm
→ 1-cell, 0-cell

Each Minterm is identified by a decimal number whose binary representation

is identical to the binary interpretation of the input values of the minterm.
Karnaugh Map
a Identification a value
a
0
F
1 0 0 of the cell 0 0 of F

1 0 1 1 1 1
F(a) =m (1)
1-cell
b
a b F
a 0 1 b0 1
0 0 0
0 0 1 a
0 1 1 0 0 1
1 0 1 1 2 3
1 1 1 1 1 0
F(a,b) = m(1,2)
 10 Map Simplification
IMPLEMENTATION OF K-MAPS
- Don’t-Care Conditions -
In some logic circuits, the output responses
for some input conditions are don’t care
whether they are 1 or 0.

In K-maps, don’t-care conditions are represented

by X’s in the corresponding cells.

Don’t-care conditions are useful in minimizing

the logic functions using K-map.
- Can be considered either 1 or 0
- Thus increases the chances of merging cells into the larger cells
--> Reduce the number of variables in the product terms
b
a
1 X X 1
a X 1
bc
c
a
F
b
c
 11 Combinational Logic Circuits

COMBINATIONAL LOGIC CIRCUITS

y y
Half Adder x y cout s
0 0 0 0 0 0 0 1
0 1 0 1 x 0 1 x 1 0
1 0 0 1 cout = xy s = xy + x y
1 1 1 0 =x  y
Full Adder
y y
x y cin cout s
0 0 0 0 0 0 0 0 1
0 0 1 0 1 0 1 c 1 0 cn-1
n-1
0 1 0 0 1 x 1 1 x 0 1
0 1 1 1 0 0 1 1 0
1 0 0 0 1 cn s
1 0 1 1 0
1 1 0 1 0 cout = xy + xcn-1+ ycin
1 1 1 1 1 = xy + (x  y)cin
s = x ycn-1+ x ycin+xycin+xycin
= x  y  cin = (x  y)  cin
 12 Combinational Logic Circuits

COMBINATIONAL LOGIC CIRCUITS

Other Combinational Circuits

Multiplexer
Encoder
Decoder
etc
 13 Combinational Logic Circuits

MULTIPLEXER

• A multiplexer selects information from an input line and directs the

information to an output line
• A typical multiplexer has n control inputs (Sn - 1, … S0) called selection
inputs, 2n information inputs (I2n- 1, … I0), and one output Y
• A multiplexer can be designed to have m information inputs with m < 2n as
well as n selection inputs
4-to-1 Multiplexer

Select Output
S1 S 0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
 14 Combinational Logic Circuits

DECODER

• Decoder - Circuits that perform decoding

• Decoding - the conversion of an n-bit input code to an m-bit output code
with n £ m £ 2n such that each valid code word produces a unique output
code
• Functional blocks for decoding are
o called n-to-m line decoders, where m £ 2n
o generate 2n (or fewer) minterms for the n input variables

2-to-4 Decoder

E A1 A0 D0 D1 D2 D3
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
1 d d 1 1 1 1
 15 Combinational Logic Circuits

ENCODER

• Encoders - Circuits that perform encoding

• Encoding - the opposite of decoding - the conversion of an m-bit input
code to a n-bit output code with n £ m £ 2n such that each valid code word
produces a unique output code
• An encoder has 2n (or fewer) input lines and n output lines which generate
the binary code corresponding to the input values
• Typically, an encoder converts a code containing exactly one bit that is 1
to a binary code corresponding to the position in which the 1 appears.

Octal-to-Binary Encoder
 16 Flip Flops

FLIP FLOPS
• Types of flip-flop
 D Flip-Flop
 T Flip-Flop
 JK Flip-Flop
 SR Flip-Flop

• Basic Flip-Flop Descriptors

 Used in analysis
 Characteristic table - defines the next state of the flip-flop in terms
of flip-flop inputs and current state
 Characteristic equation - defines the next state of the flip-flop as a
Boolean function of the flip-flop inputs and the current state
 Used in design
 Excitation table - defines the flip-flop input variable values as
function of the current state and next state
 17 Flip Flops

FLIP FLOPS DESCRIPTORS

D Flip-Flop JK Flip-Flop
• Characteristic • J K Q(t+1) Table
Characteristic Operation
D Q( 1)Table
t+ Operation
0 Reset 0 0 Q(t) No change
1 1 Set 0 1 0 Reset
0
1 0 1 Set
1 1 Q(t) Complement

• Characteristic Equation
Q(t+1) = D • Characteristic Equation
• Excitation Table Q(t+1) = J Q + K Q
• Excitation
Q(t) Q(t Table
+1) J K Operation
Q(t +1) D Operation
0 0 0 X No change
0 0 Reset
1 1 Set 0 1 1 X Set
1 0 X 1 Reset
1 1 X 0 No Change
 18 Flip Flops

FLIP FLOPS DESCRIPTORS

T Flip-Flop SR Flip-Flop
• S R Q(t+1)
Characteristic Operation
Table
• Characteristic Table
T Q(t +1) Operation
0 0 Q(t) No change
0 Q(t) No change 0 1 0 Reset
1 Q(t) Complement 1 0 1 Set
1 1 ? Undefined
• Characteristic Equation
• Characteristic Equation
Q(t+1) = T Å Q Q(t+1) = S + R Q, S.R
• Excitation Table =0
• Q(t) Q(t+
Excitation 1) S R
Table Operation
Q(t +1) T Operation
0 0 0 X No change
Q(t) 0 No change
0 1 1 0 Set
Q(t) 1 Complement
1 0 0 1 Reset
1 1 X 0 No change
 19 Sequential Circuits

SEQUENTIAL CIRCUITS - Counters

 A synchronous counter, also known as a parallel counter, all the flip-flops in

the counter change state at the same time in synchronism with the input clock
signal.
 The clock signal in this case is simultaneously applied to the clock inputs of all
the flip-flops
 20

SEQUENTIAL CIRCUITS - Counters

 A ripple counter is a cascaded arrangement of flip-flops where the output of one

flip-flop drives the clock input of the following flip-flop.
 Known as asynchronous counter or a serial counter, the clock input is applied
only to the first flip-flop, also called the input flip-flop, in the cascaded
arrangement.
 The clock input to any subsequent flip-flop comes from the output of its
immediately preceding flip-flop.