Moores Law

Gordon Moore: co-founder of Intel. Predicted that number of transistors per chip would grow exponentially (double every 18 months). Exponential improvement in technology is a natural trend: steam engines, dynamos, automobiles.

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Moores Law plot

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The cost of fabrication

Current cost: $2-3 billion. Typical fab line occupies about 1 city block, employs a few hundred people. New fabrication processes require 6-8 month turnaround. Most profitable period is first 18 months-2 years.

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Cost factors in ICs

For large-volume ICs:

packaging is largest cost; testing is second-largest cost.

For low-volume ICs, design costs may swamp all manufacturing costs.
$10 million-$20 million.

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Mask cost vs. line width

1,000,000 900,000 800,000 700,000 600,000 500,000 400,000 300,000 200,000 100,000 0 .25 micron .18 micron .13 micron .09 micron

mask cost ($)

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Field-programmable gate arrays

FPGAs are programmable logic devices:

Logic elements + interconnect. Provide multi-level logic.
LE LE LE Interconnect network LE LE LE
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FPGA-Based System Design: Chapter 1

FPGAs and VLSI

FPGAs are standard parts:

Pre-manufactured. Dont worry (much) about physical design.

Custom silicon:
Tailored to your application. Generally lower power consumption.

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Standard parts vs. custom

Do you build your system with an FPGA or with custom silicon?

FPGAs have shorter design cycle. FPGAs have no manufacturing delay. FPGAs reduce inventory. FPGAs are slower, larger, more power-hungry.

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Challenges in system design

Multiple levels of abstraction: logic to CPUs. Multiple and conflicting constraints: low cost and high performance are often at odds. Short design time: Late products are often irrelevant.

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The system design process

May be part of larger product design. Major levels of abstraction:

specification; architecture; logic design; circuit design; layout.

FPGA-based system design

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Elements of an FPGA fabric

Logic. Interconnect. I/O pins.
IOB LE LE LE IOB IOB

LE LE interconnect LE LE LE LE

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Terminology
Configuration: bits that determine logic function + interconnect. CLB: combinational logic block = logic element (LE). LUT: Lookup table = SRAM used for truth table. I/O block (IOB): I/O pin + associated logic and electronics.

FPGA-Based System Design: Chapter 1 Copyright 2004 Prentice Hall PTR

Logic element

Programmable:
Input connections. Internal function.

Coarser-grained than logic gates.

Typically 4 inputs.

Generally includes register. May provide specialized logic.

Adder carry chain.
FPGA-Based System Design: Chapter 1 Copyright 2004 Prentice Hall PTR

Example logic element

Lookup table: a
0

b
0 1 0

out
0 0 1 0 1 0 0 1

a b

0010

0
out

memory
1001

1
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Logic synthesis
How do we break the function into logic elements? How do we implement an operation within a logic element?

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Placement

Where do we put each piece of logic in the array of logic elements?

LE
LE LE

LE
LE LE

LE
LE LE
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FPGA-Based System Design: Chapter 1

Programmable wiring

Organized into channels.

Many wires per channel.

Connections between wires made at programmable interconnection points. Must choose:

Channels from source to destination. Wires within the channels.
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Programmable interconnection point

FPGA-Based System Design: Chapter 1

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Programmable wiring paths

FPGA-Based System Design: Chapter 1

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Choosing a path
LE

LE
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FPGA-Based System Design: Chapter 1

Routing problems

Global routing:
Which combination of channels?

Local routing:
Which wire in each channel?

Routing metrics:
Net length. Delay.

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Segmented wiring

Length 1 Length 2

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Offset segments

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I/O
Fundamental selection: input, output, threestate? Additional features:

Register. Voltage levels. Slew rate.

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Programming technologies

SRAM.
Can be programmed many times. Must be programmed at power-up.

Antifuse.
Programmed once.

Flash.
Similar to SRAM but using flash memory.

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Configuration

Must set control bits for:

LE. Interconnect. I/O blocks.

Usually configured off-line.

Separate burn-in step (antifuse). At power-up (SRAM).

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Configuration vs. programming

FPGA configuration:
Bits stay at the device they program. A configuration bit controls a switch or a logic bit.

CPU programming:
Instructions are fetched from a memory. Instructions select complex operations.

add r1, r2

addIR r2 r1,

memory

CPU

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Reconfiguration

Some FPGAs are designed for fast configuration.

A few clock cycles, not thousands of clock cycles.

Allows hardware to be changed on-the-fly.

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FPGA fabric architecture questions

Given limited area budget:

How many logic elements? How much interconnect? How many I/O blocks?

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Logic element questions

How many inputs? How many functions?

All functions of n inputs or eliminate some combinations? What inputs go to what pieces of the function?

Any specialized logic?

Adder, etc.

What register features?

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FPGA-Based System Design: Chapter 1

Interconnect questions
How many wires in each channel? Uniform distribution of wiring? How should wires be segmented? How rich is interconnect between channels? How long is the average wire? How much buffering do we add to wires?

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FPGA-Based System Design: Chapter 1

I/O block questions

How many pins?

Maximum number of pins determined by package type.

Are pins programmed individually or in groups? Can all pins perform all functions? How many logic families do we support?

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