Electronics Circuits Laboratory, Spring Semester 2023-24

Experiment 3B: DESIGN AND SIMULATION OF CASCADED CE-CC

AMPLIFIER
Done by: ANMOL DEEP (22IE10008)
 Objective
1. Design of directly Coupled CE-CC Amplifier
2. Observe Advantages of CE-CC Amplifier over CE Amplifier
3. CE-CC Amplifier with Resistive Load
Part B: Design and Simulation of CC-CE
Cascaded Amplifier
Circuit Diagram for CE-CC Amplifier
This is the schematic for the
Cascaded Common Emitter
Common Collector Amplifier
with self-bias configuration.
Here, we have used a 2N4124
transistor,

For operating point

configuration, we have given
the .op directive.
Operating point parameters 2N4124
For operating point
configuration, we have given
the .op directive

These are the operating point

parameters for the 2N4124
transistor
Transient Analysis Circuit Diagram
This is the schematic for the
Cascaded Common Emitter
Common Collector Amplifier
with self-bias configuration.
Here, we have used a 2N4124
transistor,

For transient analysis, .trans

command is given for
Gain-Transient Analysis for 100Hz
This is the maximum voltage
obtained without significant
distortion

For transient analysis, .trans

command is given for

The Gain is
Gain-Transient Analysis for 500Hz
This is the maximum voltage
obtained without significant
distortion.

For transient analysis, .trans

command is given for

The Gain is
Gain-Transient Analysis for 1kHz
This is the maximum voltage
obtained without significant
distortion.

For transient analysis, .trans

command is given for

The Gain is
Gain-Transient Analysis for 5kHz
This is the maximum voltage
obtained without significant
distortion.

For transient analysis, .trans

command is given for

The Gain is
Gain-Transient Analysis for 10kHz
This is the maximum voltage
obtained without significant
distortion.

For transient analysis, .trans

command is given for

The Gain is
Gain-Transient Analysis for 50kHz
This is the maximum voltage
obtained without significant
distortion.

For transient analysis, .trans

command is given for

The Gain is
Gain-Transient Analysis for 100kHz
This is the maximum voltage
obtained without significant
distortion.

For transient analysis, .trans

command is given for

The Gain is
Gain-Transient Analysis for 500kHz
This is the maximum voltage
obtained without significant
distortion.

For transient analysis, .trans

command is given for

The Gain is
Gain-Transient Analysis for 1000kHz
This is the maximum voltage
obtained without significant
distortion.

For transient analysis, .trans

command is given for

The Gain is
Gain-Transient Analysis for 2000kHz
This is the maximum voltage
obtained without significant
distortion.

For transient analysis, .trans

command is given for

The Gain is
AC Analysis Circuit Diagram
This is the schematic for the
Cascaded Common Emitter
Common Collector Amplifier
with self-bias configuration.
Here, we have used a 2N4124
transistor,

For ac analysis, .ac command

is given.
Output and Phase-Plot
This is the schematic for the
Cascaded Common Emitter
Common Collector Amplifier
with self-bias configuration.
Here, we have used a 2N4124
transistor,. Upper Cutoff
Frequency is
AC Analysis Circuit Diagram with 1nF
This is the schematic for the
Cascaded Common Emitter
Common Collector Amplifier
with self-bias configuration.
Here, we have used a 2N4124
transistor,. Here a 1nF
Capacitor is added to CE part.

For ac analysis, .ac command

is given.
Output and Phase-Plot
This is the schematic for the
Cascaded Common Emitter
Common Collector Amplifier
with self-bias configuration.
Here, we have used a 2N4124
transistor,. Here a 1nF
Capacitor is added to CE part.
Comparing with and w/o Capacitance
2N4124 2N4124

Here Gain is Increased.

Part C: CC-CE Cascaded Amplifier Driving
Resistive Load
Circuit Diagram for CE-CC Amplifier
This is the schematic for the
Cascaded Common Emitter
Common Collector Amplifier
with self-bias configuration
and resistive load of . Here,
we have used a 2N4124
transistor,

For operating point

configuration, we have given
the .op directive.
Operating point parameters 2N4124
For operating point
configuration, we have given
the .op directive

These are the operating point

parameters for the 2N4124
transistor
Output for 6mV Input
This is the schematic for the
Output of Cascaded Common
Emitter Common Collector
Amplifier with self-bias
configuration and resistive
load of . Here, we have used a
2N4124 transistor,

The Maximum swing is for this

Input.
FFT for 6mV Input
This is the schematic for the
FFT of Cascaded Common
Emitter Common Collector
Amplifier with self-bias
configuration and resistive
load of . Here, we have used a
2N4124 transistor,
Output for 7mV Input
This is the schematic for the
Output Cascaded Common
Emitter Common Collector
Amplifier with self-bias
configuration and resistive
load of . Here, we have used a
2N4124 transistor,
FFT for 7mV Input
This is the schematic for the
FFT Cascaded Common
Emitter Common Collector
Amplifier with self-bias
configuration and resistive
load of . Here, we have used a
2N4124 transistor,
Output for 8mV Input
This is the schematic for the
Output Cascaded Common
Emitter Common Collector
Amplifier with self-bias
configuration and resistive
load of . Here, we have used a
2N4124 transistor,
FFT for 8mV Input
This is the schematic for the
Output Cascaded Common
Emitter Common Collector
Amplifier with self-bias
configuration and resistive
load of . Here, we have used a
2N4124 transistor,
THANK YOU