Superscalar - Superpipelined -

Processor
By
Dr. Mausumi Maitra
Professor
Dept. of Information Technology
Govt. College of Engg. and Ceramic Technology
 Superscalar
 1st invented in 1987.

 Superscalar processor executes multiple independent

instructions in parallel.

 Common instructions (Arithmetic, Store / Load etc.) can be

initiated simultaneously and executed independently.

 Applicable to both RISC and CISC, but usually in RISC.

 Clock Cycles ------
Instructions
1 2 3 4 5 6 7 8 9

1 IF ID EX MEM WB

2 IF ID EX MEM WB

3 IF ID EX MEM WB

4 IF ID EX MEM WB

5 IF ID EX MEM WB

6 IF ID EX MEM WB

Superscalar Processor of order 2

Here 6 instructions are completed in 7 clock cycles. In the

steady state, 2 instructions are completed per clock cycle.
 Why Superscalar

 Most operations are on scalar quantities.

 Superscalar was designed to improve the performance of

these operations by executing them concurrently in
multiple pipeline.
 Superscalar Requirements

 Hardware should permit fetching of several instructions

simultaneously from instruction memory and instruction
registers.
 Data cache must also have several independent ports for
Read / Write. 64 bit data path is required for fetching two
32 bit instructions.
 Multiple execution unit is required to avoid resource
conflicts.
 Minimum extra execution unit that will be required – a
floating point arithmetic unit, an integer arithmetic unit
and a separate address calculation arithmetic unit.
 Superscalar Performance

 In superscalar multiple independent instruction pipelines

are used. Each pipeline consists of multiple stages, so that
each pipeline can handle multiple instructions at a time.
 A superscalar processor typically fetches multiple
instructions at a time and then attempt to find nearby
instructions that are independent of one another and can
therefore be executed parallelly.
 If the input to one instruction depends on the output of a
preceding instruction, then the latter instruction cannot
complete execution at the same time or before the former
instruction.
 Super Pipeline

 Super-pipeline is an alternative approach to achieve

greater performance.
 1st invented in 1988.
 Many pipeline stages need less than one clock cycle.
 It is the breaking of stages of a given pipeline into
smaller stages in an attempt to shorten the clock period
and thus enhancing the instruction throughput by
keeping more and more instructions in flight (in some
part of the pipeline) at a time.
 Superpipelined Processor

Clock Cycles -----

Instructions
1 2 3 4 5 6 7

1 IF ID EX DM WB

2 IF ID EX DM WB

3 IF ID EX DM WB

1 IF1 IF2 ID EX1 EX2 DM1 DM2 WB

2 IF1 IF2 ID EX1 EX 2 DM1 DM2 WB

3 IF1 IF2 ID EX 1 EX 2 DM1 DM2 WB

 Superpipeline Performance
 Some stages in the pipeline require less than one clock
cycle, e.g. ID and WB.

 Thus we may divide each clock cycle into two phases

and allocate intervals appropriate for each step.

 Fig. shows we have allocated full clock cycle for IF, EX

and DM steps, while half a cycle is allocated for ID and
WB steps.
 Each step is subdivided into two phases such that each
phase needs different resources, thereby resource conflicts
is avoided.

 Here instead of 7 clock cycles it requires 5 clock cycles.

 In the steady state, one instruction will take half a clock

cycle under ideal conditions.

 Very high speed processor e.g. MIPS R4000 use this

concept.

 All the hazards are applicable here also.