• Course Name: Embedded System

• Topic Name: Introduction to ARM

Dr. Karmjit Singh Sandha

Associate Professor, ECED
 Introduction
 Key Component in Embedded Systems.
 ARM cores are used in mobile phones, handheld
organizers(PDA),portable consumer devices, automobile
industry, Networking, Security Systems.
 Originally Acorn RISC Machines, but now called as
Advanced RISC Machines.
 Development started in 1985.
 Continuation of the architecture enhancements from the
original architecture.
 Over 1 billion ARM processors were sold by 2001.
ARM7TDMI was most successful ARM core.
 ARM does not fabricate silicon itself
 Features of ARM Processors
• 32 bit RISC processor.
• High Code density.( Less memory)
• Hardware Debug Technology.
• Load store architecture.
• Mostly Single Cycle Execution except variable cycle
execution for certain instructions*.
• Inline barrel shifter.
• Thumb 16 bit instruction set.
• Conditional execution *: An instruction is only executed
when a specific condition has been satisfied.
 Features Continued
• Enhanced Instructions: DSP
• Large 16 x 32 register file*.
• Uniform and Fixed op code width of 32 bits to ease
decoding and pipelining.
• Powerful indexed addressing modes.
• Simple, but fast, 2-priority-level interrupt subsystem with
switched register banks.
• Good Speed(few Mhz to Ghz) and Power consumption
ratio
• Based on Von Neumaan Architecture or Harvard
Architecture
 Architecture Revisions

• ISA : Instruction Set Architecture

• Nomenclature
• ARM {x}{y}{z}-{T}{D}{M}{I}{E}{J}{F}{S}
• X: family, y: Memory Mangmt /Protection,
• Z : Cache
• T: Thumb
• D: Debugger (on-chip debug support)
• M: Extended Multiplier (Consists Multiply instructions)
• I : Embedded ICE macrocell (Allow breakpoint watchpoint to be set)
• E: Enhanced Instructions (DSP processor)
• J: Java acceleration by Jazelle (for JAVA coding)
• F: Vector floating point unit
• S: Synthesizable version ( Core is provided as source code which can be
modified and used by EDA tools)
ARM Cores
ARM Processor Family
 ARM Processor Family

https://en.wikipedia.org/wiki/List_of_ARM_microarchitectures
• Course Name: Embedded System
• Topic Name: Architecture of ARM

Dr. Karmjit Singh Sandha

Associate Professor, ECED
Internal Architecture of ARM
 Detail of internal Registers of ARM
• There are 37 ARM registers in total of which variable
amount is available as banked registers depending on
the mode of operation.
• R13 functions always as stack pointer
• R14 functions as link register, where the core puts the
return address whenever it calls a subroutine.
• R15 is the program counter (pc) and contains the
address of the next instruction to be fetched by the
processor.
• CPSR : Current program status register
• SPSR : Saved Program status register.
 Modes of ARM Processor
• ARM has 7 modes
• Out of which 6 privileged (Allows full read write access to cspr)
1.Abort( failed attempt to access memory and/or Memory
protection)
2.Fast Interrupt request(Fast Interrupt for high speed)
3.Interrupt request(Used for general purpose interrupt handling)
4.Supervisor ( after reset, OS kernal operation)
5.System(Special version of user mode)
6.Undefined ( undefined instruction and supports software
emulation of hardware coprocessors)
• One non-privileged mode (allows read access to control field and
read write to conditional flags)
7.User mode (Normal programs and applications)
• Course Name: Embedded System
• Topic Name: Register set of ARM

Dr. Karmjit Singh Sandha

Associate Professor, ECED
Modes of ARM Processor
 Registers of ARM
• The ARM has total of 37 registers.

• Out of which 30 are general purpose

registers, 6 are status registers and one is a
program counter.

• Only fifteen of the general purpose registers

are available at any one time depending on
the processor mode.
 Registers of ARM
• There are a standard set of eight general purpose
registers that are always available (R0–R7) no
matter which mode the processor is in.
• These registers are truly general purpose, with no
special uses being placed on them by the processors’
architecture.
• A few registers (R8–R12) are common to all
processor mode with the exception of the fiq mode.
• When the processor is in the fast interrupt mode
these registers are replaced with the different set of
registers (R8_fiq – R12_fiq)
 Registers of ARM
• The general purpose register can be used to handle
8 bit bytes, 16 bit half words, or 32 bit words.
• When we use a 32 bit register in a byte instruction
only the least significant 8 bits are used.
• In a half word instruction only the least significant
16 bits are used.
• The remaining registers (R13 – R15) are special
purpose registers and have very specific roles.
 Registers of ARM

• R13 is also known as the Stack pointer, while

R14 is known as the Link Register, and r15 is
the program counter.
• The “user” (usr) and “System” (sys) modes
share the same registers.
• There are also one or two status registers
depending on which mode the processor is in.
• Current processor status register (CPSR)
holds information about the current status of
the processor (including its current mode)
 Registers of ARM

• In the exception modes there is an

additional Saved Processor Status register
(SPSR) which holds information on the
processors state before the system changed
into this mode i.e. the processor status just
before an exception.
 Stack pointer, SP or R13

• Register r13 is used as a stack pointer and is

also known as the SP register.
• Each exception mode has its own version of
r13, which points to a stack dedicated to that
exception mode.
• The stack is typically used to store temporary
values.
 The link register, LR or r14
• Register r14 is also known as the Link register or LR

• It is used to hold the return address of a subroutine.

• When an execution occurs, the exception mode’s version

of r14 is set to the address after the instruction which has
just been completed.

• The SPSR is a copy of the CPSR just before the

exception occurred.
The Program Counter, PC or r15
• Register r15 holds the Program Counter known
as the PC.

• It is used to identify which instruction is to be

performed next.

• As the PC holds the address of the next

instruction it is often referred to as an
instruction pointer.
 Current Processor Status Register
(CPSR)
• Current processor status register (CPSR)
contains the current status of the processor.
• This includes various conditional code flags
Interrupt Status Processor mode and other status
and control information.
• The exception modes also have a saved
processor status register (SPSR), that is used to
preserve the value of CPSR when the associated
exception occurs.
• Because the User and System modes are not
exception modes, there is no SPSR available.
Bit pattern Current Processor Status
Register (CPSR)
Current Processor Status Register (CPSR)

The processors’ status is split in to two distinct parts:

the User flags and the Systems Control flags.

The upper half word is accessible in User mode and

contains a set of flags which can be used to effect the
operation of a program.

Any bit not currently used is reserved for future use

and should be zero.

The I and F bits indicate if interrupts (I) or Fast

Interrupts (F) are allowed.
The system flags can only be altered when the
processor is in protected mode.

User mode programs can not alter the status

register except for the condition code flags.
Current Processor Status Register (CPSR)

The upper four bits of the status register contains a set

of four flags, collectively known at condition code.

The condition code flags are

Negative (N)
Zero (Z)
Carry (C)
Overflow (V)
The condition code can be used to control the flow of the
program execution.
 • Course Name: Embedded System
• Topic Name: Modes and Exceptions of
ARM

Dr. Karmjit Singh Sandha

Associate Professor, ECED
 Exceptions
• Exceptions are situations that stop the normal functioning of
the program.
• ARM supports seven types of exception, and provides
privileged processing modes for each type.
Exception processing modes

Exception Type Processor Mode

Reset Supervisor svc
Software Interrupt Supervisor svc
Undefined Instruction Undefined und
Prefetch Abort Abort abt
Data Abort Abort abt
Interrupt IRQ irq
Fast Interrupt FIQ fiq
 Role of Exceptions
• Reset – Can occur when the processor reset pin is
given a signal or by branching to the reset vector
address (0x0000). The first one is a hardware
reset while the second one is a software reset.
• Undefined instruction – Occurs when the
processor cannot recognize the currently
executing instruction
• Software Interrupt (SWI) – Caused by user
defined interrupts (in the program) or user
requesting to switch to more privileged modes.
SWI can be used to call privileged OS subroutines.
 Role of Exceptions
• Prefetch Abort – Occurs when an instruction is
fetched from an illegal address
• Data Abort – A data transfer instruction attempts to
load or store data at an illegal address
• IRQ – The processor’s external interrupt request pin is
asserted(LOW) and the I interrupt mask in the CPSR
is clear (enable). IRQ are assigned to general
purpose interrupts like periodic timers.
• FIQ – The processor’s external fast interrupt request
pin is asserted (LOW) and the F interrupt mask in the
CPSR is clear (enable).
• FIQ is reserved for one single interrupt source that requires
fast response time.
 Priority and vector locations of exceptions

Different exceptions are handled in different modes of the

processor. Different exceptions also have different priorities.
Mode selection using CPSR
 Handling of exception:

1.Copy the CPSR into the SPSR of the mode in

the which the exception is to be handled.
2.Change the mode bit in the CPSR .
3.Disable interrupts
4.Set link register to the return address
5.Set the program counter to the vector address
for the exception
 Leaving exception handler:
1.Move the Link Register LR (minus an offset)
to the PC.
2.Copy SPSR back to CPSR, this will
automatically changes the mode back to the
previous one.
3.Clear the interrupt disable flags (if they were
set).
 Exceptions Execution
The exception handler are located a pre-defined locations
known as Exception vectors. It is the responsibility of an
operating system to provide suitable exception handling.
• Course Name: Embedded System
Topic Name: Memory Organization

Dr. Karmjit Singh Sandha

Associate Professor, ECED
 Memory Organization
• Little and Big Endian (the bigend bit)
• Little Endian scheme: The lowest numbered byte in a word is considered
to be the least significant byte of the word and the highest numbered byte
is the most significant. Byte 0 of the memory system should be connected
to data lines 7 through 0 (D7:1) in this scheme.
 Memory Organization
• Big Endian scheme: The lowest numbered byte in a word is considered to
be the most significant byte of the word and the highest numbered byte is
the lowest significant. Byte 0 of the memory system should be connected
to data lines 31 through 24 (D31:24) in this scheme.
Memory Organization
Thanks