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Figure 1.1 Graph of an analog quantity (temperature versus time).
Copyright ©2009 by Pearson Higher Education, Inc.

Digital Fundamentals, Tenth Edition Upper Saddle River, New Jersey 07458
Thomas L. Floyd All rights reserved.
Figure 1.2 Sampled-value representation (quantization) of the analog quantity in Figure 1–1. Each value represented
by a dot can be digitized by representing it as a digital code that consists of a series of 1s and 0s.

Figure 1.3 A basic audio public address system.

Figure 1.4 Basic block diagram of a CD player. Only one channel is shown.

Figure 1.5 Logic level ranges of voltage for a digital circuit.

Figure 1.6 Ideal pulses.

Figure 1.7 Nonideal pulse characteristics.

Figure 1.8 Examples of digital waveforms.

Figure 1.9

Figure 1.10 Example of a clock waveform synchronized with a waveform representation of a sequence of bits.

Figure 1.11 Example of a timing diagram.

Figure 1.12 Illustration of serial and parallel transfer of binary data. Only the data lines are shown.

Figure 1.13

Figure 1.14

Figure 1.15 The basic logic operations and symbols.

Figure 1.16 The NOT operation.

Figure 1.17 The AND operation.

Figure 1.18 The OR operation.

Figure 1.19 The comparison function.

Figure 1.20 The addition function.

Figure 1.21 An encoder used to encode a calculator keystroke into a binary code for storage or for calculation.

Figure 1.22 A decoder used to convert a special binary code into a 7-segment decimal readout.

Figure 1.23 Illustration of a basic multiplexing/demultiplexing application.

Figure 1.24 Example of the operation of a 4-bit serial shift register. Each block represents one storage “cell” or
flip-flop.

Figure 1.25 Example of the operation of a 4-bit parallel shift register.

Figure 1.26 Illustration of basic counter operation.

Figure 1.27 Block diagram of a tablet-bottling system.

Figure 1.28 Cutaway view of one type of fixed-function IC package (dual in-line package) showing the chip mounted
inside, with connections to input and output pins.

Figure 1.29 Examples of through-hole and surface-mounted devices. The DIP is larger than the SOIC with the
same number of leads. This particular DIP is approximately 0.785 in. long, and the SOIC is approximately 0.385 in.
long.

Figure 1.30 Examples of SMT package configurations. Parts (e) and (f) show bottom views.

Figure 1.31 Pin numbering for standard types of IC packages. Top views are shown.

Figure 1.32 Typical digital oscilloscopes. Used with permission from Tektronix, Inc.

Figure 1.33 Basic comparison of analog and digital oscilloscope operation.

Figure 1.34 Block diagram of an analog oscilloscope.

Figure 1.35 Block diagram of a digital oscilloscope.

Figure 1.36 Representation of a typical digital oscilloscope front panel. Numbers below screen indicate the values
for each division on the vertical (voltage) and horizontal (time) scales and can be varied using the vertical and
horizontal controls on the scope.

Figure 1.37 Comparison of an untriggered and a triggered waveform on an oscilloscope.

Figure 1.38 Displays of the same waveform having a dc component.

Figure 1.39 An oscilloscope voltage probe. Used with permission from Tektronix, Inc.

Figure 1.40 Probe compensation conditions.

Figure 1.41

Figure 1.42 Typical logic analyzer. Used with permission from Tektronix, Inc.

Figure 1.43 Simplified block diagram of a logic analyzer.

Figure 1.44 Two logic analyzer display modes.

Figure 1.45 A typical multichannel logic analyzer probe. Used with permission from Tektronix, Inc.

Figure 1.46 Typical signal generators. Used with permission from Tektronix, Inc.

Figure 1.47 Typical DMMs. Courtesy of B+K Precision. ®

Figure 1.48 Typical dc power supplies. Courtesy of B+K Precision. ®

Figure 1.49 Illustration of how a typical logic pulser and a logic probe can be used to apply a pulse to a given
point and check for resulting pulse activity at another part of the circuit. Indications may vary depending on
manufacturer.

Figure 1.50 Programmable logic.

Figure 1.51 Block diagrams of simple programmable logic devices (SPLDs).

Figure 1.52 A typical SPLD package.

Figure 1.53 General block diagram of a CPLD.

Figure 1.54 Typical CPLD packages.

Figure 1.55 Basic structure of an FPGA.

Figure 1.56 A typical ball-grid array (BGA) package.

Figure 1.57 Basic setup for programming a PLD or FPGA.

Figure 1.58 Basic programmable logic design flow block diagram.

Figure 1.59

Figure 1.60

Figure 1.61

Figure 1.62

Figure 1.63

Figure 1.64


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Figure 1.1 Graph of an analog quantity (temperature versus time).

Copyright ©2009 by Pearson Higher Education, Inc.

Copyright ©2009 by Pearson Higher Education, Inc.

Copyright ©2009 by Pearson Higher Education, Inc.

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