STUDY OF NON CONVENTIONAL

CHANNEL
MOSFET

by:
DEBASMITA GHOSH
ROLL-14200320023
DEBJANI SATPATI
ROLL-14200320032
Under the guidance of
Dr; SWAPNADIP DE ,Associate professor
 CONTENTS
• Introduction to scaling
• Introduction to Short Channel Effects in MOSFET
• Mobility Degradation and Surface Scattering
• Hot electron effect
• Drain induced barrier lowering
• Punch through
• Single Halo MOSFET
• Double Halo MOSFET
• Model description for short channel MOSFET
• Conclusion
• Future Scope
• References
 PROGRESSES OF WORK

WORK DONE TILL DATE : We done modelling of suface potential for double
gate MOSFET in sub threshold regime. Then we done the modelling of
threshold voltage and drain current of DG MOSFET. After that we plots the
surface potential equation using MATLAB . Then plots the drain current and
threshold voltage equation using MATLAB and finally for the till date we done
comparative analysis with existing models .

REMAINING PART OF THE WORK : Preparation of research paper for

possible publication .
Introduction to Scaling
MOS transistors are scaled primarily due to Increased device packing density
and speed.

Two types of scaling are common:

 The constant field scaling
 The constant voltage scaling

 Constant field scaling warrants a reduction in the power supply

voltage as the
minimum feature size is decreased.

 Power supply voltage is not reduced in the constant voltage scaling and is
therefore the preferred scaling method since it provides voltage compatibility with
older circuit technologies.

 The disadvantage of the constant voltage scaling is that the electric field
increases as the minimum feature length is reduced, leading to the detrimental
short channel effects.
Introduction to Short Channel
Effects in MOSFET
A MOSFET device is considered to be short when the channel length is of the
same order of magnitude as the depletion-layer widths of the source and the
drain junctions.

Reduction of channel length of MOSFETs leads to the short channel effects

like:
Reduction in the threshold voltage.

 Drain Induced barrier lowering.

 Punch through effect.
 Mobility degradation.
 Hot carrier effect.
Mobility Degradation and Surface
Scattering +VGS

VDS
 Vertical electric field in a short
channel MOSFET and due to
Vertical E-Field
that surface scattering

n+ n+
 Inversion layer charge is induced
by a vertical field
P-substrate
 Surface scattering effect reduce
Inversion
mobility.As Vgs
charge layer
increases,surface mobility
Induced space
charge decreases.
Inversion layer
oxide

Drain

Space charge

Carrier surface scattering

 Hot electron
effect

• When carriers move in the electric fields that exceed the value of the velocity
saturation, they continue to acquire kinetic energy from the electric field but
their velocity is randomized by the excessive collision such that their velocity
along the electric field direction no longer increases but their random kinetic
energy does.
• A small fraction of the overall carrier population acquires a significant
energy, and these are called hot carriers
 Drain induced barrier
lowering

When the device is scaled down, the drain region moves closer to the source, and
its electric field influences the whole channel. This effect is known as drain
induced barrier lowering
 Punch through

•Punch through in a MOSFET is an extreme case of channel length

modulation where the depletion layers around the drain and the source
regions merge into a single depletion region.

•Punch through causes a rapidly increasing current with increasing drain-

source voltage.

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 Single Halo MOSFET
Source Gate Oxide Drain

Np
n+ n+
Lp

Substrate concentration Na

Increasing the substrate doping decreases the width of the junction

depletion layers and thus the short channel effects are reduced.

Increasing substrate doping only at the source ends can suppress the
short channel effects without degrading the carrier mobility. This is known
as a LAC device.
 Double Halo MOSFET
Source Gate Oxide Drain

Np Np
xj n+ L-2Lp n+
Lp Lp

Substrate concentration Na

In this case there are two pocket regions with a higher doping concentration Np at the two ends
of the channel placed symmetrically upto a distance of Lp, while a relatively lower concentration
Na in the middle portion of length L – 2Lp = La are used.

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 Double Gate MOSFET
Double gate electrically shield the channel
Gate

Electric Field
Gate Gate
Lines
Source Drain

S D S D
Gate

Gate

Gate Oxide
Gate
Electric Field
Buried Oxide Lines Buried Oxide

Source Drain

Gate
Single gate SOI Double gate SOI
Gate Oxide

The two gates are electrically connected so that they both serve to modulate the channel. Short
channel effects are greatly suppressed in such a structure because the two gates very effectively
terminate the drain field lines, preventing the drain potential from being felt at the source end of
the channel.

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Model description for short channel MOSFET

MOSFET STRUCTURE

The mosfet structure is used to develop and implement the model.

Gauss law is applied to a rectangular box in the depletion region of the
MOSFET and also mobile charge carriers are neglected. The following
equation is derived , Ꜫsi (d ^ 2 *Ѱ_{s})/(d * x ^ 2) – (C ox/ Y d) Ѱ s =qN a
– (C ox/ Y d) V gs
An empirical model is proposed for this as Yd(x)=(ax+b)^2
with the source and drain end values given by,

Y_{d}(0) =X j + 2 Ꜫ si =X j +X rs

Yd(L)=Xj + =Xj +Xrd respectively , Xj is the junction depth,

Xrs = and

Xrd =
Using Yd(x)= in (1) we get

- Ѱ s = - V’ GS ……………………….(3)

The complete solution of (3) is given by

)𝛃

X rs > L – X rd (short channel MOSFET ) : in general, this case

arises when the source and the drain religious are close to
each other .
Region I : = 0 < x<== / 2 : the corresponding y values are = { + }/𝜍s and
y2 = Y sd with the end potentials V1 = + and to be evaluated .

Region – II : : the corresponding y and the end potential values are

same as in region I .

Region –III : < x <= : The corresponding y values are and ={} with end
potentials to be evaluated and ++V .
%surface potential versus Channel %surface potential versus Channel
Length plot for two different Vds for Length plot for two different acceptor
%70nm technology node. %ion concentration(Na).

%surface potential versus Channel

Length plot for two different channel
%lengths.
 Surface potential v/s channel length
Surface potential v/s channel length plots plots for Vds=1v for 100nm
for 70nm technology & 180nm technology.
for Vds=1.2v & 0.1v.

Surface potential v/s chanel length plots for 130nm

technology device for
a)Np=1.8*10^18/cm3,Na=9*10^17/cm3 and
b)Np=9*10^17/cm3,Na=4*10^17/cm3
Surface potential v/s channel length Surface potential v/s chanel
plots for 130nm technology node length plot for Vds=0.25v &1v
with Vds=0.25 & 1v for 100nm technology node.

Surface potential v/s channel length plot for

130nm technology node for a)Np=2*10^18 /cm3,
% Lp=16nm,Na=9*10^17 /cm3 and b)Np=10^18
/cm3,Lp=24nm,Na=4*10^17 /cm3.
Conclusion
In this thesis the main focus has been on the modeling and the influence of
depletion layers around the source and the drain regions on the sub-threshold
characteristics of a short-channel Single Gate Dual Material Double Halo and
Double Gate Dual Material Double Halo MOSFETs. An analytical model for
subthreshold surface potential in a short channel Single gate Double Halo Double
Gate MOS transistor has been developed by solving the pseudo-2D Poisson’s
equation, formulated by applying Gauss’s law to a rectangular box in the channel
covering the entire depletion layer depth. The model has been able to predict an
increased influence of the junction depletion regions for smaller channel length or
higher drain/source bias voltages due to increased charge sharing. The model is
also applied to find the sub-threshold surface potential for Double Gate Double
Halo Dual Material Gate MOSFET.
Future Scope
• The non conventional device structure like channel and gate engineer Double
GateMOSFET, Surrounding Gate MOSFET etc. can be model using suitable
analytical technique. I am planning to find an analytical model of surface
potential, drain current and threshold voltage using high-k gate di electric. This
characteristic parameter can be obtain for non conventional MOSFET to validate
our model. The software tool to be used for validation is Synopcis – TCAD. The
propose analytical model will be ploted using Matlab.
References
[1] Suitability of High-K Gate Dielectrics On The Device Performance And
Scalability Of Nanoscale Double Gate Finfets With Quantum Modeling”, By
Subha Subramaniam, Sangeeta M.Joshi, R.N.
[2] “Modelling Of Sub Threshold Surface Potential for Short Channel Double
Gate Dual Material Double Halo Mosfet” by Debarati Das
[3] “Role Of High-K Materials In Nanoscale Tm-Dg Mosfet: A Simulation Study
“proposed by K.P Pradhan, P.K Agarwal, P.K Sahu and S.K Mohapatra of
National Institute of Technology, Rourkela, Odisha
[4] “Optimum High-k Oxide for the Best Performance of Ultra-scaled DoubleGate
MOSFETs” by M. Salmani-Jelodar, H. Ilatikhameneh, S. Kim, K. Ng, and G.
Klimecky.
[5] “A Germanium NMOSFET Process Integrating Metal Gate and Improved Hi-K
Dielectrics” written by Chi on Chui, Hyoungsub Kim, Paul C. McIntyre and
Krishna C. Saraswat .
Thank
You
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