Polymorphism:

The ability of object to take many forms is called polymorphism.

• By default only child handle is assigned to parent handle.

• By declaring class with virtual keyword, base class can be overwrite for different functions.
• Extended class handle can be assigned to base class handle.
• Virtual declaration of base class makes its child members visible to it.

Polymorphism means having many forms. A base class handle can invoke methods of its child class
which has the same name. Hence, an object can take many forms.

1. As we know, the derived class object can override methods of its base class. Similarly, the
base class object can also override the method of one of the child classes. It means a base
class method has different forms based on derived class implementation.
2. To use many forms of the method, the virtual keyword must be used in the method
definition.
Steps for Polymorphism:

1. Create a base/parent class with virtual keyword.

2. Create child classes.
3. Create memory for child class.
4. Assign child handle to parent handle.
5. Access extended class using base class.
Data Encapsulation and Hiding in SV:
Data encapsulation is a mechanism that combines class properties and methods.

Data hiding is a mechanism to hide class members within the class. They are not accessible outside
of class scope. This avoids class member modification outside the class scope and its misuse.

By default, all class members are accessible with class handles in SystemVerilog. To restrict access,
access qualifiers are used.

Local Access Qualifier

If a class member is declared as a local, they will be available to that class alone. The child classes
will not have access to a local class member of their parent class.

Protected access Qualifier

As discussed earlier, local access qualifiers can not be accessed outside of the class scope. But
sometimes it is required to provide class member access to derived classes. This access is provided
by a protected access qualifier.

A protected class member can not be accessed outside class scope except access by their child
classes.
Interface:
Unlike Verilog that has module ports for communication, SystemVerilog provides an interface
construct that simply contains a bundle of sets of signals. This encapsulates signals and
communicates with design, testbench components.

Advantages of SystemVerilog interfaces

1. In Verilog for the addition of new signals, it has to be manually changed everywhere from
where the module has been instantiated. System Verilog made it easier to add new signals
in the interface block for existing connections.
2. It has increased re-usability across the projects.
3. A set of signals can be easily shared across the components bypassing its handle.
4. It provides directional information (modports) and timing information (clocking blocks).
5. Interfaces can contain parameters, variables, functional coverage, assertions, tasks and
functions.
6. Interfaces can contain procedural (initial and always blocks) and continuous (assign)
statements.
Syntax:
interface <interface_name>;
...
endinterface
Writing Interface

Basic Interface: Parameterized Interface:

interface bus (input clk); interface bus #(parameter WIDTH = 32)(input clk);
logic [31:0] addr; logic [WIDTH-1:0] addr;
logic [31:0] data; logic [WIDTH-1:0] data;
logic en; logic en;
endinterface endinterface
interface fa_if; module half_addr(input a, b, output so, co);
logic a, b, c; assign so = a^b;
logic s_out, c_out; assign co = a & b;
endinterface endmodule

module tb_top; module full_adder(fa_if inf);

fa_if inf(); wire s0, c0, c1;
full_adder fa(inf); half_addr HA1 (inf.a, inf.b, s0, c0);
half_addr HA2 (s0, inf.c, inf.s_out, c1);
initial begin
$monitor("a=%b b=%b c=%b, sum=%b, carry= assign inf.c_out = c0 | c1;
%b",inf.a,inf.b,inf.c,inf.s_out,inf.c_out); endmodule
inf.a = 1; inf.b = 0; inf.c = 0;
#1;
inf.a = 1; inf.b = 0; inf.c = 1; Output:
#1;
inf.a = 0; inf.b = 1; inf.c = 1; a=1 b=0 c=0, sum=1, carry=0
end a=1 b=0 c=1, sum=0, carry=1
endmodule a=0 b=1 c=1, sum=0, carry=1
SystemVerilog modport:
Within an interface to declare port directions for signals modport is used. The modport also put
some restrictions on interface access.

Syntax:
modport <name> ( input <port_list>, output <port_list>);

Advantages of using modports:

1. Modport put access restriction by specifying port directions that avoid driving of the
same signal by design and testbench.
2. Directions can also be specified inside the module.
3. Modport provide input, inout, output, and ref as port directions
4. Multiple modports can be declared for different directions for monitor and driver.
 SystemVerilog Clocking Block:

To specify synchronization scheme and timing requirements for an interface, a clocking block is
used. The testbench can have multiple clocking blocks but only one clocking block per clock.
The clocking block can be declared in the program, module, or interface.

Syntax:
clocking <clocking_name> (<clocking event>);
Default input <delay> output <delay>;
<signals>
endclocking

Advantages of Clocking Block:

1. It provides a group of signals that are synchronous with a particular clock in DUT and testbench.
2. Provides a facility to specify timing requirements between clock and signals.
Clocking Events:
To synchronize the clocking block, a clocking event is used. The clocking event governs the timing of all signals
mentioned in that clocking block. All input or inout signals are sampled on the occurrence corresponding clock event.
Similarly, output or inout are also driven by the occurrence of the corresponding clock event.

Example: @(posedge clk) or @(negedge clk)

Clocking Skew:
The input or output clocking block signals can be sampled before or after some time unit delay known as clocking
skew. It is declared as:
default input #2 output #3;
Input clocking skew: #2
Output clocking skew: #3

1. This means input signals is sampled #2 time unit before the clocking event and output signals are driven, #3 time
units after the clocking event.
2. The input and output skews must be either parameter or constant. By default, input and output skews are 0 time
units if not specified. It is possible to specify particular time units otherwise by default skews are considered based
on the timescale in the current scope.

Note: In the clocking block, the direction of signals is mentioned w.r.t. testbench (not w.r.t. DUT).
Clocking Block Declarations
//1 //4
clocking cb @(negedge clk); clocking cb @(posedge clk);
default input #2 output #3; default input #1ps output #4; // explicit declaration of time
input ... unit
output ... input ...
endclocking output ...
endclocking
//2
clocking cb @(clk); // clocking event without edge //5
//outputs are driven on negedge clk clocking cb @(posedge clk);
default input #2 output negedge; default input #1ps output #4; // explicit declaration of time
input ... unit
output ... input #2ps <signal_name>;
endclocking input #3 output #4 <signal_name>;
endclocking
//3
clocking cb @(posedge clk);
default input #1 output negedge;
//outputs are driven on negedge clk
input ...
output ...
endclocking
Virtual Interface
An interface represents signals that are used to connect design modules or testbench to the DUT and commonly
known as a physical interface. The design and physical interface are static in nature. Hence, they can not be used
dynamically. In modern testbench, randomized class objects are used and connect to the design dynamically. Hence, to
bridge the gap between the static world of modules and the dynamic world of objects, a virtual interface is used as a
pointer or handle for an actual interface.

Syntax: virtual<interface_name> <interface_instance>

Features of the virtual interface:

1. The virtual interface must be pointed to the actual or physical interface. This is also known as virtual interface
initialization.
2. Before accessing or driving to the virtual interface, it must be initialized otherwise it will cause a fatal run-time
error as it has a null value.
3. The virtual interfaces can be passed to the functions and tasks as an argument.
4. The virtual interface can be declared as class properties and it initialized an argument to the constructor or
procedurally.
5. The dynamic object can be assigned to the virtual interface. Also, interface values are recorded in the dynamic
object by accessing the virtual interface.
6. They can be assigned to another virtual interface having the same type using ‘=’ operator.
 SystemVerilog DPI
Direct Programming Interface (DPI) allows users to establish communication between foreign languages and
SystemVerilog. It has two separate layers as a foreign language layer and a SystemVerilog layer which are completely
isolated. DPI allows having a heterogeneous system that connects and efficiently connects existing code written in
other languages.
DPI also allows calling functions and tasks from other languages or vice-versa using import/ export methods. These
methods can communicate with the help of arguments and return value.
Import method
SystemVerilog can call functions or tasks (methods) implemented in a foreign language, such methods are called
import methods

import “DPI-C” function <return_type> <function_name> (<arguments if any>)

SV File: C File:
module tb;
#include <stdio.h>
import "DPI-C" function void addition(int a, int b);

initial void addition(int a, int b) {

begin printf("Addition of %0d and %0d is %0d\n", a, b, a+b);
$display("Before add function call"); }
addition(4,5); Output:
$display("After add function call"); Before add function call
end Addition of 4 and 5 is 9
After add function call
endmodule
Export method
A foreign language can call functions or tasks (methods) implemented in SystemVerilog, such methods are called
export methods

export "DPI-C" function <function_name>

C File: SV File:
#include <stdio.h> module tb;
//#include <svdpi.h>
export "DPI-C" function addition; // This is not a function prototype
extern void addition(int, int); import "DPI-C" context function void c_caller();

void c_caller() { function void addition(int a, b);

printf("Calling addition function from c_caller\n"); $display("Addition of %0d and %0d is %0d\n", a, b, a+b);
addition(4, 5); endfunction

} initial
begin
c_caller();
end
endmodule
Output:

Calling addition function from c_caller

Addition of 4 and 5 is 9
 Extern method in Classes
An extern method provides a facility for class methods to define them outside of the class body.
If the method definition is lengthy (many lines of code inside a method), the extern method provides better
readability and cleaner implementation of the class.

Extern Methods:
1. Method definition and declaration should have the same number of argument lists, data types, and argument
names.
2. For the extern function return type should be the same if used.
3. If the definition of method (task or function) is written outside the body of class then the method is called
external method.
4. To do this, need to declare the method with an “extern” keyword in the class body.
5. The extern qualifier indicates that the body of the method(its implementation) is to be found outside the class
declaration.
6. Before the method name the class name should be specified with a class scope resolution to specify to which
class the method corresponds to.
7. Number of arguments, argument name and argument type should match between method declaration and
method definition.

Note: An extern method is accessed using scope operator(::)

class transaction;
bit [31:0] data; module class_example;
int id; transaction tr;

extern function void display(); initial begin

extern task delay(); tr = new();
endclass
tr.data = 100;
function void transaction::display(); tr.id = 1;
$display("data = %0d and id = %0d", data, id);
endfunction tr.display();
tr.delay();
task transaction::delay(); end
#50; endmodule
$display("Time = %0.0t, delayed data = %0d",
$time, data);
endtask

Output:
data = 100 and id = 1
Time = 50, delayed data = 100