Verilog-based Automatic Bus Ticketing system
Absract --This paper offers a comprehensive synthesis,
combining practical investigations, theoretical analyses,
and literature reviews to delve into the research of a bus
automatic ticket-selling system using Verilog HDL. In the
design of this bus ticketing system, the central goals are
convenience, speed, and simplicity, all geared towards
optimizing time-saving for passengers during the ticket
purchasing process. The study commences with an
examination of the historical and global landscape of bus
ticketing systems before delving into the core components
of such systems. To realize the design, Quartus II 13.1
development software is employed for schematic input.
The resulting bus automatic ticket selling system
comprises essential modules, including the ticket
selection module, coin calculation module, change
processing module, and display interface module. This
paper also encompasses simulations of these modules
within the Quartus II 13.1 environment.
Keywords- Verilog HDL, Ticket Selection, Coin
Calculation, Quartus II
I. INTRODUCTION
Officially known as the Pandit Nehru Bus Station but
often shortened to PNBS, this bustling hub is India's largest
and Asia's second-largest bus terminal. Nestled on the south
side of Vijayawada and adjacent to the Krishna River, PNBS
reigns supreme as the state's premier road transport connector,
linking Andhra Pradesh's cities and towns with ease.
The advancement of automatic ticketing systems in
urban buses is intrinsically linked to the development of the
road transport field. This progress fosters a reciprocal
relationship, where advancements in ticketing systems play
a crucial role in shaping road transport efficiency, and vice
versa.
Customers can purchase tickets, board buses, and leave
stations using the service system known as AFC (Automatic
Fare Collection). It serves as a crucial benchmark for
assessing the quality of urban bus transportation. This is A
system that operates automatically, that combines automatic
control and computer network connection. At the same time,
we have seen the science and technology of integrated
circuits advance quickly in recent years, particularly with
regard to PLG circuits. Additionally, the Verilog
Programming language includes built-in benefits including
precise timing, process-independent design, flexibility, and
ease of use. Efficiency of the design can also be increased by
using the Verilog Programming language. Therefore, Verilog
Programming language serves as the foundational language
for creating the bus's computerized ticketing system.
II. DESIGN PRINCIPLE
A. Verilog HDL Language
Verilog Hardware Description Language (HDL) is a
language used to model and simulate digital electronic
systems. It allows designers to describe the behavior and
structure of digital circuits and systems. Verilog supports
both behavioral and structural modeling, is concise and
expressive, and is primarily used for simulation. It is well-
suited for describing parallel operations in digital hardware,
supports hierarchical design, and is event-driven. Verilog
code can be divided into synthesizable and non-synthesizable
sections, and it has been standardized under IEEE 1364.
Various versions and extensions, such as SystemVerilog,
have been developed to enhance its capabilities. Verilog is
widely used in digital design for FPGA and ASIC design,
embedded system development, verification, and testing.
B. Quartus II Software
Quartus II is a software tool developed by Intel (formerly
Altera) for designing, simulating, and programming Field-
Programmable Gate Arrays (FPGAs) and Complex
Programmable Logic Devices (CPLDs). This platform offers
a holistic integrated development environment (IDE) for
digital design, encompassing all stages—from design entry
and simulation to synthesis, physical layout and routing,
timing analysis, and configuration. Quartus II also supports
IP integration, offers debugging tools like SignalTap Logic
Analyzer, and is compatible with a wide range of Intel FPGA
and CPLD devices. It's widely used by digital designers for
FPGA and CPLD development and comes with extensive
documentation and support resources.
C. FPGA buy, use qua_1, qua_2 as the function. qua_1 denotes buying
one ticket, while qua_2 denotes buying two tickets.
It is a versatile semiconductor device that distinguishes
itself from traditional chip design methods. Unlike
conventional chip design, which is often confined to specific
research and technology domains, FPGA offers a unique
advantage. It allows for optimization and design
enhancements within a product's related technical fields by
leveraging a particular chip model.
FPGAs are no longer just niche chips for specialized
applications. They stand at the forefront of a paradigm shift,
where software and hardware converge and semi-custom
reigns supreme. It encompasses digital management modules,
embedded units, and various other components. Notably,
FPGA's versatility sets it apart from Application-Specific
Integrated Circuits (ASICs), as it continues to find
widespread utility, particularly in the realm of the
communication industry.
Fig .1.1. Selection Module
By conducting thorough market research and examining
global suppliers of FPGA-related products, coupled with a Module output: PATH denotes the selected line's output,
consideration of India's unique circumstances and its world- which is sent as input to the modules responsible for
leading enterprises, we can gain valuable insights into the processing, calculating amounts, and displaying information.
trends and directions of FPGA-related products' The total amount owed (COST) is entered into the processing
development. India's scientific and technological and balance calculation modules for computation,
advancements depend on this comprehensive analysis to Simultaneously, the system transmits the selected quantity
guide and drive its progress, ultimately elevating its global PIN to the display module for verification. This will be
technological standing. utilized in the computation of the appropriate recovery
amount. We'll take your fare (PRI), whip it through the
III. DESIGN CONTENT calculation and display machine, and show you the result.
This paper primarily focuses on the design of an B. Rupees Calculation Module
automated ticket-purchasing system that empowers
passengers to effortlessly acquire tickets through Module in: Initiate a system reset by pressing the RD
straightforward operations. This automatic ticketing system, button. Passenger interaction with this button triggers a
designed for effortless passenger experience, exclusively system reset. The core of a sequential logic circuit is the
accepts 10-rupees and 20-rupees notes. Its core architecture clock signal, or CLK (Clock). The signals of input 5 rupee
comprises four key modules: selection module, rupees are denoted by FIVE_IN, and those of input 10 rupee by
calculation module, return processing module and interface TEN_IN.
display module.
A ticket selection module's purpose is to offer clients
ride route choosing options, as the name would imply.
Passengers will insert money after the route is chosen.
Simultaneously, the data from both the money input
processing and route selection modules will be channeled to
the calculation module and displayed on the interface. The
return calculation module computes the money a client
should receive in return for their investment and as the
calculation module finishes its work, the interface module Fig.1.2. Rupees Calculation Module
jumps into action, displaying the results for the customer to The output of the module is represented by the letters
see. FIVE_OUT, TEN_OUT, and OUT, which stand for the ten
A. Ticket Selection Module digits, total, and the output, respectively, of the total quantity
of gold coins. This number goes to the return calculating
Module input: When pressed, the reset button (RD) can module to see how many rupees you get.
perform the function of zero clearing. The core of a
sequential logic circuit is the clock signal, or CLK (Clock). C. Return Processing Module
path_ 1 、 path_ 2. They are both effective and will Module in: Initiate a system reset by pressing the RD
realize the line selection function when one of them is button. Passenger interaction with this button triggers a
high-level effective. The No. 1 busline is 01, and the No. 2 system reset. Synchronized by the CLK signal, the passenger
busline is the route that the customer chooses (10). pri3, One proceeds to press the final confirmation button, or FINISH,
of the two, pri4 and pri5, is configured as the ticket after inserting their coin. The module function determines
price selection function at a high level. When choosing how whether to sell the ticket to the client upon customer
many tickets to
interaction, the signal transitions to a high state.
Simultaneously, a function of change calculation will be
executed. To determine if a ticket is issued, PATH_IN is used.
Which ticket to sell is determined by PRI_ IN. The total
amount payable is entered as COST_IN, while the entire
amount invested is entered as COIN_IN.
(2)Selector: Module 6 counter is scanned by the nixie
tube. Based on the input that the counter sent. The selector
acts as a gatekeeper, determining which data will be
presented as output.
(3)Decoder: The function of the seven-segment nixie tube
is indicated. To display the necessary number, it converts
a four-bit binary code to a seven-bit binary code.
E. Top Level File

Fig.1.3. Return Processing Module

Module output: CHANGE output pin relays the result,
prompting the display module to update its indication on how
much should be given to the passengers. According to
VALID_TIC[5:0], six distinct ticket types are associated
with the illumination of six individual light-emitting diodes,
allowing for precise identification of each ticket issue. The
primary function of DISP_TIC is to regulate whether the
circuit's diode emits light or not. When the LED illuminates,
it indicates that the customer needs to receive change. If the
LED is in the off state, no change operation is required. Fig.1.5. Top level File

D. Display Interface Module
The 6-out-of-1 selector, decoder, and module 6 counter
make up the display function module. The primary function
is to clearly illustrate the chosen path, corresponding ticket
price per unit, number of tickets acquired, overall expense
incurred, and any recoverable amount.
The coin calculation, change processing, ticket selection, and
display interface modules make up this top level file. It is the
top-level file for the display interface, coin computation,
change processing, and ticket selection.
IV.Design Results
A. Selection Module Simulation
Following is the selection module simulation diagram.
The priority,path and quantity pins are logical at high level,
as shown by the simulation diagram, the system
acknowledges that passengers have chosen line 1, indicating
a ticket price of 10 rupees for two tickets. The anticipated
outcomes are attained.

Fig.1.4. Display Interface Module

Fig1.6. Simulated Waveform
(1) Module 6: This design implements a clock-driven three-
bit binary counter, that represents the entire 0–5 counting B. Rupees calculation and processing module simulation
process, ranging from 000 to 101. Reaching a count of 101
Analysing the simulation diagram reveals that the high
plus 1 exceeds the counter's capacity, resulting in a carry
state configuration of the designated denomination pins
signal and a complete reset to zero. After scanning the nixie
translates to an investment of 15 rupees. The simulation was
tube, each of the six data from the selector is chosen and
successful and yields the anticipated results
produces output separately.
.

Fig1.7. Simulated Waveform
C. Rupees calculation and return processing module
The simulation indicates line 2 as the chosen bus path, a
5-rupee ticket price, and a 10-rupee payment. This
corresponds to the fifth ticket type, prompting the system to
update the fare to 5 rupees upon receiving the full payment.
Fig1.8. Simulated Waveform
D. Display interface module
Validating the design against the initial specifications is
achieved by examining the simulation diagram's outputs. The
observed range of hexadecimal values (0 to 5) generated in
response to the clock signal input verifies our design's
accuracy and consistency.
Fig1.9. Simulated Waveform
E. 6 out of 1 selector
Fig1.10. Simulated Waveform
It is possible to determine that the design is successful by
analyzing the simulation diagram, which shows that the six
data points will likewise be output in accordance with
changes in the selection signal.
V. Conclusions
Verilog HDL's dominance as a language for hardware
design is further solidified by its role in this bus ticketing
system, alongside the robust capabilities of the Quartus II
13.1 (64- bit) platform. This union represents the cutting
edge of design and development.
This design is an automated ticketing system for buss. The
system automates the entirety of the ticket purchasing
process, encompassing path selection, path display, payment
processing, return dispensing, and ticket printing. We can
look into the real circumstances surrounding the bus ticket
vending machine as part of the graduation comprehensive
training, which gives us a better understanding and
assessment of the real situation of the design. We can also
identify individuals who will not be able to conduct online
electronic transactions conveniently given the real situation,
or who will not be able to conduct online transactions under
unforeseen circumstances like a dead phone or a limited
network.
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