VLSI IMPLEMENTATION OF A HIGH SPEED

AND AREA EFFIECIENT N-BIT DIGITAL CMOS

COMPARATOR
PROJECT ASSOCIATES UNDER THE GUIDANCE OF

A. HARIKA CHOWDARY (20K61A0404) MR. T. PRASAD M.E

N. LAKSHMI NARAYANA (20K61A0497) ASSISTANT PROFESSOR

D. BHAVANI (20K61A0436)

K. BABLU NAGA SIVA (20K61A04H2)

LIST OF CONTENTS
• Introduction
• Abstract
• Work progress towards proposed system
• Literature Survey
• Motivation & Problem Statement
• Existing Method and Results
• Proposed Method and Results
• Comparisons of both methods and Results
• Applications
• Conclusion
• Outcomes mapped with PO’s
• Project Applications
• References
 ABSTRACT
The most fundamental arithmetic comparisons in a digital comparator involve comparing two numbers that are greater
than, less than, or equal to each other. While doing enormous level arithmetic comparisons, a digital comparator needs
more space, which results in higher power consumption and a delayed response. This can be solved by using Nbit
comparator with two modules using 45GPDK CMOS Technology. An N-bit comparator can operate at extremely high
speeds having effective area and power dissipation which can also reduce the proposed comparator design's space and
power consumption. The proposed model is carried out bitwise starting with the least significant bit and working way
up to the most significant bit. This process continues only if the bits are equivalent, and the result is what is known as a
Parallel prefix tree structure. Two distinct modules make up the proposed comparator structure methodology which
are Final unit (FU) and comparison evaluation unit (CEU) are the first and second units, respectively. Validated findings
from the methodical organization of repeating logic cells are used to create tree structures. The FU module
authenticates the result by relying on CEU results. The proposed architecture's use of structured VLSI technique
enables area derivation using analytical method relating transistor count and total delay, which can be understood in
terms of operand bit width. While running the virtuoso simulations at 1 GHz with both old model and 45GPDK CMOS
technology, it has been found that the design has been enhanced the operating speed by 31.92% while reducing power
usage by 77.76%.
 INTRODUCTION

Some of them include Applications Digital picture processing, pattern recognition and matching, arithmetic
classification, data compression, and neural networks. networks are all examples of artificial intelligence. networks.
more with built-in testing features, signature analyzers, and jitters measurement). Digital comparator is a
fundamental building block in each of the aforementioned applications. The major element employed is an optimized
comparator design for improving general-purpose memory addressing logic in computer architecture. widespread
implementations of computation-based architectures. As a result, there is a requirement for maximum efficiency in
terms of velocity, size, and strength. Some comparator designs employ dynamic logic to adhere to the standard of
lower power usage. However, due to limitations, limited speed, and low noise margin, dynamic designs become
difficult to implement. Some of the other ideas are accomplished utilizing flat adder circuits with subtractors in
combination with specialized logic circuits.
 WORK PROGRESS TOWARDS PROPOSED SYSTEM:
Month Plan of action

November Study on various comparator Design techniques, various methods for implementing comparator.

December Study on Real time applications related to three stage comparators and done Literature survey
also Studied an application paper - software based comparator implementation for existing
method.
.
January Implementation of existing method and gathered its results.

February Started implementing proposed method architecture.

March Implementation of proposed method and gathered its results and Compared regular
implementation and comparator architecture results and started documentation.
Literature SURVEY
Title of the Project Authors Technology Objectives Advantages Dis advantages

Scalable, High-Speed, Digital Piyush 180nm cmos High speed High speed, low power delay
Comparators With N Bits Of Tyagi ,Rishikesh technology consumption
Data Pandey

Hammering Weight Parhami, B 90nm innovative counting High speed High delay.
Comparators For Binary based techniques for
Vectors Using Parallel comparing hamming
Up/Down Counters And
Accumulation

A Rapid Tag Comparator For Suzuki, H.Kim, 0.18um/1.8 v Reduce the parasitic High speed The dynamic lock
64-Bit Microprocessors Based C.H.Roy, K capacitance contains a large
On Diode Partitioned Domino. number of gated
transistors. limited
operational velocity

A Parallel Binary Comparator Chua, C., Kumar, R., 0.18um/1.8 v Transistor count is less. Low power The layout contains a
With N Bits That Consumes Sireesha, B consumption . substantial number of
Less Power And Room Design transistors.
And Analysis For Analog
Integers
Title of the Project Authors Technology Objectives Advantages Dis advantages

An Area- And Power-Efficient Boppana, N., Ren, 90nm/1.2v Area efficient digital Area, power , Delay are Extensive area planning
64-Bit Digital Comparator S. comparator. improved. for expansive
operands. Limited
operating velocity

An Enhanced Parallel Binary Chua, Kumar, 0.18um/1.8 v Area efficient power, delay, and area High power dissipation.
Comparator Design And comparator
Simulation.

A Quick And Efficient Z
Comparator.
Hensley J., Singh 0.18um/1.8 v It reuses the More energy Very sluggish transistor
M., Lastra, A current ,prevents the full efficient,faster count, power
discharge of integration dissipation, and delay
capacitors by cmos are reported for 24bit
comparison

A Complementary And Floating Stine, J.E., Schulte, 0.35um/3.3 v Less transistor count. High speed. Delay is high.
Point Comparator. M.J.
Title of the Project Authors Technology Objectives Advantages Dis advantages

High-Speed Low-Power Belluomini,W ., 180nm High speed circuit High speed, low power High delay.
Applications Requiring The Jmasek,d. Nartin, design. consumption
Design Of Dynamic Logic A.K
Circuits With A Small Number
Of Switches.
Using A Parallel Prefix Tree, A Hafeez, Ross, and 0.15um/1.5 v High speed CMOS High speed. High number of
Scalable Digital CMOS Parhami (B.) comparator. transistors, limited
Comparator. power efficiency
MOTIVATION:

CMOS N-bit digital Using comparators is essential for this project. Two binary numbers used, and compared based on their
magnitude. There is a possibility that one of the two numbers will be bigger, less, or equal to the other. A digital circuit known
as a digital comparator performs the operation of comparing two binary numbers. The digital comparator is the backbone of
many different types of designs. output is derived from a process that includes comparison. This output is used to determine
the final findings

problem statement:
Digital comparator is a fundamental building block in many applications. The major element employed is an
optimized comparator design for improving general-purpose memory addressing logic in computer architecture.
As a result, there is a requirement for maximum efficiency in terms of velocity, size, and strength. Some
comparator designs employ dynamic logic to adhere to the standard of lower power usage. However, due to
limitations, limited speed, and low noise margin, dynamic designs become difficult to implement. Some of the
other ideas are accomplished utilizing flat adder circuits with subtractors in combination with specialized logic
circuits.
EXISTING METHOD BLOCK DIAGRAM:

The complete process of comparison is divided into five sets, in which CEM contains sets 1–4 and FM contains only set
5. All the sets in the design are placed in four hierarchal prefix orders according to their functionality; therefore, the
output of each set in this approach serves as the input of another set with an exclusion of set 1, whose outputs act as
the inputs of sets 2 and 3.
EXISTING METHOD SIMULATION AND RESULT:
BLOCK DIAGRAM OF PROPOSED METHOD
The sketch of the proposed comparator containing 4 bits is
shown below. This comparator performs comparison between
two binary numbers whose bits are represented as A3A2A1A0
and B3B2B1B0. In this model first comparison is performed
between most significant bits and proceeds to next bits only
when the bits are equal . Firstly most significant bits A3 and B3
are compared, if A3 greater than B3 then it results as A greater
than B, if A3 less than B3 it results as A less than B and if A3
equal to B3 then comparison is proceeded toward next most
significant bits A2 and B2 and if A2 greater than B2 then it
results as A greater than B , if A2 less than B2 then it results as A
less than B and if A2 is equal to B2 then it proceeds to the next
most significant bit. The process continues till the least
significant bit.
SIMULATOR WITH 4-BIT COMPARATOR CIRCUIT

Figure : proposed schematic of 4 Bit Comparator.

PROPOSED RESULTS

Figure 3: : proposed schematic of 4 Bit Comparator simulation

PROPOSED RESULTS

Figure 4: Dynamic power 791.30micor watt

PROPOSED RESULTS

Figure 5: Static power 22.20 nano watt

PROPOSED RESULTS

AVARGE POWER 236.4 MICRO WATT

DELAY 334.3 PICO SECONDS

COMPARATION OF BOTH METHODS:

EXISTING METHOD PROPOSED METHOD

1- 3 input NAND -6T = 6 transistor XNOR-3T*4 =12Transistor

1-4 input NAND-8T = 8 Transistor Inverter 2T*4 =8Transistor
1-5 input NAND-10T = 10 Transistor 2 input AND 1*6T =6Transistor
1-6 input NAND -12T =12T Transistor 3 input AND 1*8T =8Transistor
2-2 input NOR – 4T*2 =8T Transistor 4 input AND =10Transistor
1- 5 input AND = 13 Transistor 5 input AND =12T transistor
2 input XOR-XNOR-14T*4 =56 Transistor 4 input AND =10Transistor
4 input OR = 10 Transistor
2 input NOR =4 Transistor

Total =113 transistor Total =80 Transistor

COMPARATION OF RESULTS:

Delay No.of
Power
S.NO Method (nsec Transistor
(nW)
) s (area)

Existing Method
1 121.97 140.73 175
[8]

Existing Method
1 58.97 70.73 113
[6]

Proposed
2 01.53 50.02 80
Method [3]
APPLICATIONS:
• Processing of image in digital form
• Recognition and matching of patterns
• Sorting arithmetically
• Compression of data and neural network and Applications of test
circuits.
• Signature analyzers and jitters measurement
• Analog-to-digital converters (ADCs)
• As well as relaxation oscillators.
CONCLUSION:
A scalable comparator is opted in this study employing comparative evaluation and
modules. Parallel prefix tree structure is accomplished by using reiterated logic cells,
which are a regular structure in the CEM. Using regular structure for any arbitrary bit
widths, the characteristic predictions of proposed comparator is evaluated. It was
found that incorporating 45GPDK CMOS resulted in the working frequency being
highest with the least amount of delay and the lowest amount of power dissipation.
Because of these benefits, the opted comparator is preferred for a variety of
applications, including scientific calculations and memory addressing logic.
OUTCOMES MAPPED WITH PO’S
•PO1: Engineering knowledge
Apply knowledge of mathematics, science, engineering
fundamentals and an engineering specialization to the solution of complex
engineering problems.
•PO2: Problem analysis
Identify, formulate, research literature and analyze complex
engineering problems reaching substantiated conclusions using first
principles of mathematics, natural sciences and engineering sciences .
•PO3: Design/development of solutions
Design solutions for complex engineering problems and design system
components or processes that meet specified needs with appropriate
consideration for public health and safety, cultural, societal and environmental
considerations

•PO4: Conduct investigations of complex problems

Research based knowledge and research methods including design of
experiments, analysis and interpretation of data and synthesis of information
to provide valid conclusions.
•PO5: Modern tool usage
Create, select and apply appropriate techniques, resources and modern
engineering and IT tools including prediction and modeling to complex
engineering activities with an under- standing of the limitations
•PO6: The engineer and society
Apply reasoning informed by contextual knowledge to assess societal,
health, safety, legal and cultural issues and the consequent responsibilities
relevant to professional engineering practice.
•PO7: Environment and sustainability
Understand the impact of professional engineering solutions in
societal and environmental contexts and demonstrate knowledge of
and need for sustainable development

•PO8: Ethics
Apply ethical principles and commit to professional ethics and
responsibilities and norms of engineering practice
PO9: Individual and team work
Function effectively as an individual, and as a member or
leader in diverse teams and in multidisciplinary settings
•PO10: Communication
Communicate effectively on complex engineering activities
with the engineering community and with society at large, such as
being able to comprehend and write effective reports and design
documentation, make effective presentations and give and receive
clear instructions
•PO11: Project management and finance
Demonstrate knowledge and understanding of engineering and
management principles and apply these to one’s own work, as a
member and leader in a team, to manage projects and in
multidisciplinary environments
•PO12: Life-long learning
Recognize the need for and have the preparation and ability to
engage in independent and life- long learning in the broadest context
of technological change
REFERENCES
1. Piyush Tyagi ,Rishikesh Pandey.,'high-speed area efficient scalable Nbit digital
comparators. IET Circuits Devices Syst., 2020, Vol. 14 Iss . 4, pp.450-458

2. Parhami, B.: ‘Efficient hamming weight comparators for binary vectors based on
accumulative and up/down parallel counters’, IEEE Trans. Circuits Syst., 2009, 56,
(2), pp. 167–171

3. Suzuki, H., Kim, C.H., Roy, K., et al.: ‘Fast tag comparator using diode partitioned
domino for 64 bit microprocessor’, IEEE Trans. Circuits Syst. I, 2007, 54, (2), pp.
322–328
4. Hensley, J., Singh, M., Lastra, A., et al.: ‘A fast, energy-efficient z comparator.’
Proc.
ACM Conf. Graphics Hardware, Los Angeles, California, 2005, pp. 41–4
5. Stine, J.E., Schulte, M.J.: ‘A combined two`s complement and floatingpoint comparator’.
Proc.int.symp.Circuot systems, 2005, pp.89-92

6. Belluomini,W., Jmasek,d., Nartin, A.K, et al.: ‘Limited switch dynamic logic circuits for
high-speed low-power circuit design’, IBM J.Res.Dev., 2006,50,(2-3),pp.277-286
7. Lam,H.M., Tsui,C.Y.: ‘A mux-based high performance single-cycle CMOS comparator’,
IEEE Trans . Circuits. Syst.II, 2007,54,(7),pp.591-595

8. Frustaci, F.,Perri, S., Lanuzza,M., et al.: ‘Energy-efficient singleclock-cycle binary

comparator’, Int.J.Circuit Theory Appl., 2012,40(3),pp. 237-246
• [9] Chua, C., Kumar, R.: ‘An improved design and simulation of lowpower and
area- efficient parallel binary comparator’, Microelectron. J., 2017, 66, pp. 84–88

• [10] J. D. Bruguera and T. Lang, Multilevel reverse most-significant carry

computation, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 9, no. 6, pp.
959962, Dec. 2001.

• [11] J. Hensley, M. Singh, and A. Lastra, (2005), A fast, energy- efficient z-

comparator, in Proc. ACM Conf. Graph. Hardw, pp. 41 44.

• [12] B. Parhami, Efficient hamming weight comparators for binary vectors based on
accumulative and up/down parallel counters, IEEE Trans. Circuits Syst., vol. 56, no. 2,
pp. 167171, Feb. 2009.
THANK YOU…