CH.5. Data Converters & PLDs

Unit-5
Data Converters & PLDs
Presented By: Ms.C.M.Maind

Lecturer in E & TC Department
AISSMS’S POLYTECHNIC PUNE
1
Digital Techniques(DTE-22320) Ms.C.M.Maind
Digital Techniques(DTE-22320)
Ms.C.M.Maind 2
Digital-to-Analog Converter (DAC)
• A digital-to-analog converter (DAC or D-to-A) is a device
that converts a digital (usually binary) code to an analog
signal (current, voltage, or electric charge). An analog- to-
digital converter (ADC) performs the reverse operation .
• Basic ideal operation The DAC fundamentally converts

finite-precision numbers (usually fixed-point binary
numbers) into a continuously varying physical quantity,
usually an analogue electrical voltage.
Ms.C.M.Maind 3
Ms.C.M.Maind 4
Ms.C.M.Maind 5
Ms.C.M.Maind 6
Ms.C.M.Maind 7
Ms.C.M.Maind 8
Ms.C.M.Maind 9
Ms.C.M.Maind 10
Ms.C.M.Maind 11
Ms.C.M.Maind 12
Ms.C.M.Maind 13
Ms.C.M.Maind 14
Ms.C.M.Maind 15
Ms.C.M.Maind 16
Ms.C.M.Maind 17
• DAC Characteristics:
1. Resolution
2. Offset Error
3. Gain Error
4. Relative Accuracy
• DACs are used in many other applications, such
as voice synthesizers, automatic test system, and
process control actuator.
• In addition, they allow computers to
communicate with the real (analog) world.
Ms.C.M.Maind 18
Ms.C.M.Maind 19
PLD
Ms.C.M.Maind 20
Ch.4 Sequential logic circuits
Some important points
Ms.C.M.Maind 21
Ms.C.M.Maind 22
Timing Diagram
Ms.C.M.Maind 23
Ms.C.M.Maind 24
Truth Table & Timing Diagram
Ms.C.M.Maind 25
Ms.C.M.Maind 26
Ms.C.M.Maind 27
Ms.C.M.Maind 28
Ms.C.M.Maind 29
Ms.C.M.Maind 30
Ms.C.M.Maind 31
Ms.C.M.Maind 32
Gated or Clocked SR Flip-Flop
Ms.C.M.Maind 33
Ms.C.M.Maind 34
Ms.C.M.Maind 35
Ms.C.M.Maind 36
•The D flip-flop is widely used. It is also known as a "data" or
"delay" flip-flop.
•The D flip-flop captures the value of the D-input at a definite
portion of the clock cycle (such as the rising edge of the clock).
• That captured value becomes the Q output.
• At other times, the output Q does not change.
• The D flip-flop can be viewed as a memory cell.
Ms.C.M.Maind 37
a) Symbol b) D Flip-Flop using NAND gate
Ms.C.M.Maind 38
Qn+1=D
Ms.C.M.Maind 39
• The basic S-R NAND flip-flop circuit has many
advantages and uses in sequential logic circuits but it
suffers from two basic switching problems.
1. the Set = 0 and Reset = 0 condition (S = R = 0)
must always be avoided
2. if Set or Reset change state while the enable (EN)
input is high the correct latching action may not occur
• Then to overcome these two fundamental design
problems with the SR flip-flop design, the JK flip

Flop was developed.
Ms.C.M.Maind 40
Cont…
• The sequential operation of the JK flip flop is exactly

the same as for the previous SR flip-flop with the
same “Set” and “Reset” inputs. The difference this
time is that the “JK flip flop” has no invalid or
forbidden input states of the SR Latch even
when S and R are both at logic “1
• Both the S and the R inputs of the previous SR

bistable have now been replaced by two inputs called
the J and K inputs, respectively after its inventor Jack
Kilby. Then this equates to: J = S and K = R.
Ms.C.M.Maind 41
S=J.Q’n
R=K.Qn
Ms.C.M.Maind 42
Ms.C.M.Maind 43
•The T or "toggle" flip-flop changes its output on each
clock edge, giving an output which is half the frequency of
the signal to the T input.
• It is useful for constructing binary counters, frequency
dividers, and general binary addition devices. It can be

made from a J-K flip-flop by tying both of its inputs high.
Ms.C.M.Maind 44
High
Ms.C.M.Maind 45
Ms.C.M.Maind 46
Race Around Condition In JK Flip-flop –
For J-K flip-flop, if J=K=1, and if clk=1

for a long period of time, then Q output
will toggle as long as CLK is high, which
makes the output of the flip-flop unstable
or uncertain. This problem is called race
around condition in J-K flip-flop.
Ms.C.M.Maind 47
Ms.C.M.Maind 48
Ms.C.M.Maind 49
Master-Slave JK Flip Flop
Ms.C.M.Maind 50
•The initial state of the flip-flop would be uncertain as it
may be in the SET state, (Q = 1) or it may be in the RESET
state, (Q = 0).
• In many conditions it is initially Set or Reset the Flip-
Flop i.e the initial state of the FF is to be assigned.
• Obviously this uncertainty in its switching is undesired
as in the majority of applications we require the output to
be set in a predefined state, either SET or RESET ready to
accept data.
• But we can overcome this uncertainty with the
conversion of flip-flops using two additional
asynchronous inputs referred to
as Preset (PR) and Clear (CLR) as shown below in the S-R
Flip-Flop
Ms.C.M.Maind 51
Ms.C.M.Maind 52
The most common applications of flip – flops
are
1.Counters
2. Registers
3.Frequency Divider circuits
4.Data transfer
5.Used as memory element & Delay element
Ms.C.M.Maind 53
Ms.C.M.Maind 54
Timing Diagram
Ms.C.M.Maind 55
Ms.C.M.Maind 56
Truth Table & Timing Diagram
Ms.C.M.Maind 57
Ms.C.M.Maind 58
Ms.C.M.Maind 59

CH.5. Data Converters & PLDs

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

CH.5. Data Converters & PLDs

Uploaded by

Copyright:

Available Formats

Unit-5

Data Converters & PLDs

Presented By: Ms.C.M.Maind

• Basic ideal operation The DAC fundamentally converts

Some important points

•The D flip-flop captures the value of the D-input at a definite

• That captured value becomes the Q output.

• At other times, the output Q does not change.

• The D flip-flop can be viewed as a memory cell.

problems with the SR flip-flop design, the JK flip

• The sequential operation of the JK flip flop is exactly

• Both the S and the R inputs of the previous SR

dividers, and general binary addition devices. It can be

For J-K flip-flop, if J=K=1, and if clk=1

You might also like

CH.5. Data Converters &amp; PLDs

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

CH.5. Data Converters &amp; PLDs

Uploaded by

Copyright:

Available Formats

Unit-5

Data Converters & PLDs

Presented By: Ms.C.M.Maind

• Basic ideal operation The DAC fundamentally converts

Some important points

•The D flip-flop captures the value of the D-input at a definite

• That captured value becomes the Q output.

• At other times, the output Q does not change.

• The D flip-flop can be viewed as a memory cell.

problems with the SR flip-flop design, the JK flip

• The sequential operation of the JK flip flop is exactly

• Both the S and the R inputs of the previous SR

dividers, and general binary addition devices. It can be

For J-K flip-flop, if J=K=1, and if clk=1

You might also like

CH.5. Data Converters & PLDs

CH.5. Data Converters & PLDs