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Vlsi Lec1
Vlsi Lec1
ECE 4103
Course conductor
Ratio less
Runs faster
The difference of the voltage between high and low logic levels
decreases at each stage since pass transistors have some resistance and
do not provide level restoration. Each transistor in series is less
saturated at its output than at its input. If several devices are chained in
series in a logic path, a conventionally constructed gate may be required
to restore the signal voltage to the full value. By contrast,
conventional CMOS logic switches transistors so the output connects to
one of the power supply rails (resembling an open collector scheme), so
logic voltage levels in a sequential chain do not decrease.
5V 0V
5V 0V
D S
V
GS > V t
Suppose Vt=1V
No discharge path for capacitor
Vt=1
3V
5V
Vt=1
5V
4V
5V 4V 4V
4V
5V 3V 3V
Vt=1
4V
5V
4V
5V 3V 3V
Vt=1
VDD
o/p
A O/P
0V AND gate
Implementing logic gates using MUX
Implementing logic gates using MUX
Implementing logic gates using MUX
Implementing logic gates using MUX
Implementing logic gates using MUX
Implementing logic gates using MUX
Implementing logic gates using MUX
Implementing logic gates using MUX