Microprocessor

 Unit 2: Bus Cycles and System Architecture

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 Unit 2:
Bus Cycles and System Architecture

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 Unit 2:
Bus Cycles and System Architecture

Initialization

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 Initialization
• After a signal on the RESET pin, certain registers of 80386 are
set to predefined values.

• These values are adequate to enable execution of a bootstrap

program.

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 Processor State after RESET
• Contents of EAX depends on results power-up self test

• Self-test may be requested externally by assertion of BUSY# at the end of

RESET (EAX=0 if the 80386 passed the test, else 80386 unit is faulty)

• If self-test is not requested , EAX is undefined

• DX holds a component identifier and revision number

(DH=3, indicates 80386, DL=unique identifier of the revision level)

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 Processor State after RESET
• Control Register 0 (CR0) contains

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 State of flags and other registers

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 Functional Pin Diagram

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 Pin Description Table

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 Pin Description Table (Cont…)

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 I/O Organization

The 80386 allows input/output to be performed in either of two

ways:
a. By means of a separate I/O address space (using specific I/O
instructions)

b. By means of memory-mapped I/O (using general purpose

operand manipulation instructions )

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 a) Separate I/O address space
(An Isolated I/O)
 I/O devices treated separately from memory.
• Hardware and software architecture of
8088/8086 support separate memory I/O
address space.

 M/IO- signal is always low when 80386 is executing

these instructions.

 Can be treated as either independent byte-wide I/O

ports or word-wide I/O ports.

 Page 0:
• Certain I/O instructions can only perform
operations to ports in this part of the address
range.
• Other I/O instructions can input/output data for
ports anywhere in the address space.
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 a) Separate I/O address space
(An Isolated I/O)
Advantages: -
 1 MByte memory address space is available for use
with memory.
 Special instructions have been provided in the
instruction set of 8088/8086 to perform isolated
I/O input and output operations.
 These instructions have been tailored to maximize
I/O performance.

Disadvantages: -
 All input and output data transfers must take place
between AL or AX register and the I/O port

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 b) Memory-mapped I/O
I/O devices is placed in memory
address space of the
microcomputer.
• The memory address space is
assigned to I/O devices.

• look at the I/O port as though it is

a storage location in memory.

• Make use of instructions that

affect data in memory rather than
special input/output instructions.

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 b) Memory-mapped I/O
Advantages:
 Many more instructions and addressing
modes are available to perform I/O
operations.
 I/O transfers can now take place
between I/O port and internal registers
other than just AL/AX.

Disadvantages:
 Memory instructions tend to execute
slower than those specifically designed
for isolated I/O.
 Part of the memory address space is lost

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 Memory Organization (Memory Banks)
• 80386DX has 32 bit address bus so it can access upto 4G-bytes of
memory location.
• Address ranges from 00000000H through FFFFFFFFH and 80386DX
can access data in this memory as byte, word or double word.
• Words are accessed from two consecutive memory locations.
• To implement this entire memory is divided into four independent
byte-wide memory banks: Bank0 to Bank3.
• Each bank is 1G-byte in size.
 Memory Organization (Memory Banks)
• Bank 0, bank1, bank 2, bank 3 are selected using byte enable signals
̅B̅̅ E̅ 0, ̅B̅̅ E̅ 1, ̅B̅̅ E̅ 2, ̅B̅̅ E̅ 3 signals respectively.
 Memory Organization (Memory Banks)
• Address lines A31-A2 are connected in parallel to all memory banks which make it possible to
access 1G-byte of memory.
• MOV WORD PTR DS: [2000H], 678H This instruction writes 78 to address 2000H and 56 to
address 2001H
• Similarly, when 80386 accesses Dword from address divisible by 4, it uses four consecutive
memory locations. This works fine when 80386 accesses even byte in case of word access and
address divisible by 4 in case of Dword access, since address on the A31-A2 lines is same for
word as well as Dword access.
• The data transfers using such addresses are called Aligned transfers. But to access word from odd
address or to access Dwords from address not divisible by 4 unaligned 80386 faces problem in
placing the correct address on the address bus. This problem is solved by replacing two address
pins AO and Al with four byte enable pins.
 I/O Instructions

There are two classes of I/O instruction:

1. Those that transfer a single item (byte, word, or doubleword)
located in a register.

2. Those that transfer strings of items (strings of bytes, words, or

doublewords) located in memory.

These are known as "string I/O instructions" or "block I/O

instructions".

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 Register I/O Instructions

• The I/O instructions IN and OUT

are provided to move data
between I/O ports and the EAX
(32-bit I/O), the AX (I6-bit I/O), or
AL (8-bit I/O) general registers.

• IN and OUT instructions

addresses I/O ports either
directly, with the address of one of
up to 256 port

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 Block I/O Instructions

• The block (or string) I/O instructions INS and OUTS move blocks of
data between I/O ports and memory space.

• Block I/O instructions use the DX register to specify the address of a

port in the I/O address space.

• Block I/O instructions use either SI or DI to designate the source or

destination memory address.

• For each transfer, SI or DI are automatically either incremented or

decremented as specified by the direction bit in the flags register.

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 Read and Write Cycles
• Data transfers occur as a result of bus cycles,
classified as read or write cycles.
• Two choices of address timing are
dynamically selectable: non-pipelined, or
pipelined.
• After a bus idle state, the processor always
uses non-pipelined address timing.
• However, the NA# (Next Address) input may
be asserted to select pipelined address
timing for the next bus cycle.
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• When pipelining is selected and the
Intel386 DX has a bus request pending
internally, the address and definition of the
next cycle is made available even before the
current bus cycle is acknowledged by
READY#.
• Terminating a read cycle or write cycle, like
any bus cycle, requires acknowledging the
cycle by asserting the READY# input.
• Until acknowledged, the processor inserts
wait states
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Basic memory Read & Write Cycles with Timing Diagram

• The internal and external bus operations of 80386 are synchronized

by clock signal
• The 80386 perform variety of machine (bus) cycles in response to
internal requirements and external requirements.
• There are seven types of machine (bus) cycle/operations.

1. Memory read 2. Memory write

3. I/O read 4. I/O write
5. Instruction fetch 6. Interrupt acknowledge
7. Halt/Shut down
 Bus cycles of 80386
• In each machine cycles corresponding status signals are activated.
• The memory read and memory write machine cycles can be locked
to prevent another bus master from using the bus
• In each machine cycles corresponding status signals are activated.
• The memory read and memory write machine cycles can be locked
to prevent another bus master from using the bus.
 Bus cycles of 80386
• Seven types of machine (bus) cycles/operations.
1) Memory read
2) Memory write
3) I/O read
4) I/O write
5) Lestruction fetch
6) Interrupt acknowledge
7) Halt/Shut down
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Bus Cycles of 80386

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 System Clock
• System clock syrchronizes the internal and external bus
operations in the 80386DX.
• The 80386DX can operate on four different clock speeds
1. 80386DX - 16 (16 MHz)
2. 80386DX - 20 (20 MHz)
3. 80386DX - 25 (2s MHz)
4. 80386DX- 33 (33 MHz)
• Operating frequency of the 80386DX is half of, the CLK2
frequency.
• Therefore, CLK2 of an 80386DX - 20 is driven by 40 MHz
signal.
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28
 Bus states
• Each machine (bus) cycle consists of at least two bus states
T1 and T2,
• and each bus state consists of two CLK cycles.
1. During the first bus state (T1), address and bus status pin are
active.
2. During the second bus state (T2), actual data lransfer takes
place.
• The 80386 DX can perform two types of machine cycles :
1. Nonpipelined
2. Pipelined.

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 Dynamic Bus Sizing
• Dynamic data bus sizing is a feature allowing direct processor
connection to 32-bit or 16-bit data buses for memory or I/O.
• A single processor may connect to both size buses
• Transfers to or from 32 to 16 bit ports are supported by dynamically
determining the bus width during each machine cycle.
• The 80386DX microprocessor's bus size 16 (BS-16 [Bar/Complement]) )
input is used to inform the 80386DX at the currently addressed
device is a 16-bit device rather than a 32-bit device‘

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 Nonpipelined Bus Cycle

During T1, the 803B6DX sends the address, bus status signal and control
signals.
In case of write cycle, data to be output is also send on the data bus,
during T1.
After address access time, read or write data transfer takes place over the
data bus. 31

This activity is carried out in T2.

 Pipelined Bus Cycle
• Pipelining allows machine cycles to be overlapped.
• The main advantage of pipelining is that it increases the
amount of time required for the memory or I/O device
to respond.
• This time is also referred as access time.
• The 80386DX implements pipelining by overlapping
addressing of the next bus cycle with the data transfer of
previous bus cycle.

Here, address becomes valid in T2 state of the previous

bus cycle, and the data transfer for address takes place in
T2-state of the current bus cycle.

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• IMP Internet Protocol address: address An + 1 becomes valid
during T2 of the current bus cycle and actual data transfer
for address An + 1 takes place in T2 state of the next bus
cycle.
• If the processor is 80386DX-20 then one T-state time is 50
ns.
• In pipelined bus cycle the access time for memory and I/O
device is 100 ns whereas access time for memory and l/O
device in nonpipelined bus cycle is approximately 50 ns.

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34
 Non-Pipelined Read Cycle
The sequence of events for the
nonpipelined read cycle:
1. The read operation starts at the beginning of
phase in the T1 state of the bus cycle.
2. In this phase, 80386DX sends the address on
the address bus and enables signals(BE0 (Bar) -
BE3 (Bar)) according to data transfer type.
3. In the same phase, it activates ADS (Bar) signal
to indicate valid address is placed on the
address bus.
4. In phase 1 of T1 - state it also activates the
bus cycle definition signals : M/IO, D/C and
W/R. 35
 Non-Pipelined Read Cycle
5. At the beginning of phase 1 of T2 state,
external device activates BS16 (BAR) signal.
6. Then samples this signal in the middle of
phase 1 of T2-state.
• 32-bit data transfer: If BS16 (BAR) =1
• 16-bit data transfer: If BS16 (BAR) =0
7. The 80386 DX does this data transfer in
phase 2 of T2-state.
8. At the end of phase 2 of T2-state the
READY (BAR) signal is sampled.
9. The logic 1 on this signal inserts wait
state in the current bus cycle to extend
the bus cycle. 36
 Non-Pipelined Read Cycle
10. The LOCK (Bar) signal low
indicates that it is bus
locked cycle.
11. If bus cycles are locked the
other bus master is not
allowed to take control of
the bus between two
locked bus cycles.

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 Non-Pipelined Write Cycle
The sequence of events for the
nonpipelined read cycle:
1. It is similar to nonpipelined read
cycle.
2. The write operation starts at the
beginning of phase 1 in the T1 state of
the bus cycle.
3. In this phase, 80386DX sends the
address on the address bus and
enables signals BE0(Bar) -BE3(Bar)
according to data transfer type.
4. After sending address in the same
phase it activates its ADS(Bar) signal to
indicate valid address is placed on 38
the address bus.
 Non-Pipelined Write Cycle
10. In phase 1 of T1-state it also activates
the bus cycle definition signals M/IO,
D/C and W/R
11. At the beginning of phase 2 of T1-state,
it sends data on the data bus. This
data remains valid until the start of
phase 2 of the T1-state of the next bus
cycle.
12. At the end of phase 2 of T1- state,
ADS(Bar) is returned to its inactive logic
1 states.
13. The address bus, byte enable pins, and
bus status pins remain active through
the end of the write cycle. 39
 Non-Pipelined Write Cycle
10. In the middle of phase
1 of T2-State,
80386DX samples
BS16(Bar) input.
11. If this signal is high,
80386 DX does the
32-bit data transfer
otherwise 80386DX
performs 16-bit data
transfer.

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 Non-pipelined read & write cycles
• At the end of the second bus state
within the bus cycle, READY# is
sampled

• If asserted the bus cycle terminates

• Else the cycle continues another bus

state (a wait state) and READY# is
sampled again at the end of that state.

• This continues indefinitely until the

cycle is acknowledged by READY#
asserted.

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 Pipelined read & write cycles

• In the pipelined bus cycle

the address for the next
bus cycle is sent during
the T2 - state of the
current cycle.
• NA (next address) signal
initiates address
pipelining.

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 Pipelined read & write cycles
• It then samples NA signal at
the beginning of phase 2 of
any T state in which ADS is
not active, specifically.
 In the second T-state of a non-
pipelined address cycle
 In the first T-state of a
pipelined address cycle
 In any wait state of a non-
pipelined address or pipelined
address cycle unless NA has
already been sampled active 43
 Pipelined read & write cycles
The NA(Bar) is tested as 0
(active) during T2 of cycle
2 which ensures that
80386DX has to execute
next cycle as pipelined bus
cycle.
The cycle 2 (nonpipelined read
cycle) is also extended
with one wait state
because READY pin is not
active,
in wait state, the valid address
for the next bus cycle is
sent on the address bus as
next bus cycle is pipelined
bus cycle.
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 Pipelined read & write cycles
The next cycle (cycle 3) is
pipelined write cycle.
In this, data is sent on the data
bus in phase 2 of T1p-state
and remains valid for the
rest of the cycle.
The READY signal is sampled at
the end of T2p - state.
As it is low, write cycle is
completed without wait
state.

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 Pipelined read & write cycles

The next cycle (cycle 4) is

pipelined read cycle.
In this, READY signal is
tested 0 at the end of
phase 2 of T2p - state.
This means that read cycle is
completed without
wait state.
It is important to note that
due to pipelined address
cycle, access time is
extended and one state
(T-wait) of read cycle is
saved

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 Unit 2:
Bus Cycles and System Architecture

System Architecture

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 Systems Registers
• EFLAGS

• Memory Management Registers

• Control Registers

• Debug Registers

• Test Registers

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 Systems Registers
 EFLAGS

• Memory Management Registers

• Control Registers

• Debug Registers

• Test Registers

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 EFLAGS

System Flags of EFLAG REGISTER

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 Systems Registers
• EFLAGS

 Memory Management Registers

• Control Registers

• Debug Registers

• Test Registers

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 Memory-Management Registers
• Four registers of the 80386 locate the data structures that control segmented
memory management:
 GDTR Global Descriptor Table Register
 LDTR Local Descriptor Table Register

• These registers point to the segment descriptor tables GDT and LDT.

• IDTR Interrupt Descriptor Table Register

This register points to a table of entry points for interrupt handlers (the IDT).

• TR Task Register
This register points to the information needed by the processor to define the
current task.

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System Registers
• GDTR (Global Descriptor Table Register)
• IDTR (Interrupt Descriptor Table Register)
• LDTR ( Local Descriptor Table Register )
• CR0 - CR3 ( Control Registers )
• TR ( Task Register)
• DR0 - DR7 (Debug Registers)
• TR6 - TR7 (Test Registers)
GDTR and IDTR
• These registers hold:
• 32-bit linear base address and
• 16-bit limit of GDT and IDT
respectively.
• GDT segments are global to all tasks in
the system.
• IDT is used to locate Gates in
Interrupt/Exception handling.
LDTR
• LDTR ( Local Descriptor Table Register ) is a 16-bit register always
points to GDT to access LDTD ( Local Descriptor Table Descriptor ) in
turn responsible for allocating and accessing local memory via
LDT( Local Descriptor Table ).
 Systems Registers
• EFLAGS

• Memory Management Registers

 Control Registers

• Debug Registers

• Test Registers

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 Control Registers

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Control Registers

• Intel386 DX has three control registers of 32 bits, CR0, CR2 and CR3,
to hold machine state of a global nature
• These registers along with System Address Registers hold machine
state that affects all tasks in the system.
• To access Control Registers, load and store instructions are defined.
Control Register (CR0)
CR0 : Machine Control Register

• CR0 contains 6 defined bits for control and status purposes.

• The low-order 16 bits of CR0 is defined as Machine Status Word
• To operate only on the low-order 16-bits of CR0, LMSW and SMSW
instructions are used.
• For 32-bit operations the system should use MOV CR0, Reg
instruction.
CR0 : Machine Control Register

• PG (Paging Enable, bit 31):the PG bit is set to enable the on-chip

paging unit. It is reset to disable the on-chip paging unit.
• R (reserved, bit 4):This bit is reserved by Intel. When loading CR0 care
should be taken to not alter the value of this bit.
CR0 : Machine Control Register

• (TS Bit, Task Switched) : TS is automatically set whenever a task

switch operation is performed.
• (EM Bit, Emulate Coprocessor) :
This bit is set to cause all coprocessor opcodes to generate a Coprocessor
CR0 : Machine Control Register

• MP Bit, Monitor Coprocessor) :

• The MP bit is used with TS bit to determine if the WAIT opcode will generate a
Coprocessor Not Available fault (exception 7).
• When both MP = 1 and TS= 1, the WAIT opcode generates a trap which
checks for the coprocessor availability.
• (PE Bit, Protection Enable) :
• The PE bit is set to enable the Protected Mode.
• If PE is reset, the processor operates in Real Mode.
Control Registers

• CR1 : Reserved :CR1 is reserved for use in future Intel processors

• CR2 : Page Fault Linear Address:CR2 holds the 32-bit linear address
that caused the last page fault detected.
 Control Registers

• CR3 : Page Directory Base Address:

• physical base address of the page directory table, always page-aligned (4
Kbyte-aligned).
• Thus the lowest twelve bits of CR3 are ignored.
• A task switch through a TSS invalidates all page table entries in paging
unit cache.
 Systems Registers
• EFLAGS

• Memory Management Registers

• Control Registers

 Debug Registers

• Test Registers

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 Debug Registers
• Six registers: to control debug
features
• Accessed by variants of the MOV
instruction
• debug registers are privileged
resources

Registers are:
 Debug Address Registers (DRO-
DR3)
 Debug Status Register (DR6)
 Debug Control Register (DR7)

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Debug Registers
• Debugging of 80386 allows data access breakpoints as well as code
execution breakpoints.
• 80386 contains 6 debug registers to specify
• 4 breakpoints
• Breakpoint Control options
• Breakpoint Status
Debug Registers

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 Linear Breakpoint Address
Registers
• The breakpoint addresses specified are 32-bit
linear addresses
• While debugging, Intel 386 h/w continuously
compares the linear breakpoint addresses in
DR0-DR3 with the linear addresses generated
by executing software.

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 Debug Control Register

• LENi(i=0 - 3): Breakpoint Length Specification

Bits:
• 2 bit field for each breakpoint
• Specifies length of breakpoint fields
• The choices of data breakpoints are 1byte,
2bytes & 4bytes
• For instruction execution breakpoint, the
length is 1(beginning byte address)
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LENi Encoding
 Debug Control Register

• RWi(i=0 - 3): Memory Access Qualifier Bit

• 2 bit field for each breakpoint
• Specifies the type of usage which must occur
inorder to activate the associated breakpoint

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Debug Registers

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 Debug Control Register

• GD: Global Debug Register Access Detect

• Debug registers can only be accessed in real mode or
at privilege level 0 in protected mode
• GD bit, when set, provides extra protection against
any Debug Register access even in Real Mode or at
privilege level 0 in Protected Mode.

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 Debug Control Register
• GD: Global Debug Register Access Detect
• This additional protection feature is provided to guarantee
that a software debugger can have full control over the
Debug Register resources when required.
• The GD bit, when set, causes an exception 1 fault if an
instruction attempts to read or write any Debug Register.
• The GD bit is then automatically cleared when the exception
1 handler is invoked, allowing the exception 1 handler free
access to the debug registers.

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 Debug Control Register

• GE and LE bit: Exact data breakpoint match, global and

local
• If either GE or LE is set, any data breakpoint trap will be reported
exactly after completion of the instruction that caused the operand
transfer.
• LE bit is cleared during task switch and is used for task-local
breakpoints.
• GE bit is unaffected during a task switch and remain enabled during
all tasks executing in the system.
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 Debug Control Register

• Gi and Li(i=0 - 3): Breakpoint Enable, global and local

• If either Gi and Li is set then the associated
breakpoint is enabled.

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Debug Status Register
• A Debug Status Register allows the exception 1 handler to easily
determine why it was invoked.
• It can be invoked as a result of one of several events:
1) DR0 Breakpoint fault/trap.
2) DR1 Breakpoint fault/trap.
3) DR2 Breakpoint fault/trap.
4) DR3 Breakpoint fault/trap.
5) Single-step (TF) trap.
6) Task switch trap.
7) Fault due to attempted debug register access when GD = 1.
 Debug Status Register

• Bi : Debug fault/trap due to breakpoint 0 -3

• Four breakpoint indicator flags, B0-B3, correspond
one-to-one with the breakpoint registers in DR0-
DR3.
• A flag Bi is set when the condition described by DRi,
LENi, and RWi occurs.

80
 Debug Status Register

• BD : Debug fault due to attempted register access

when GD bit is set
• This bit is set if the exception 1 handler was invoked
due to an instruction attempting to read or write to
the debug registers when GD bit was set.

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 Debug Status Register

• BS : Debug trap due to single step

• This bit is set if the exception 1 handler was invoked
due to the TF bit in the flag register being set

82
 Debug Status Register

• BT : Debug trap due to task switch

• This bit is set if the exception 1 handler was
invoked due to a task switch occurring to a task
having an Intel386 DX TSS with the T bit set.

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 Systems Registers
• EFLAGS

• Memory Management Registers

• Control Registers

• Debug Registers

 Test Registers

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 Test Registers
• Two test registers are provided for the purpose of testing.

• TR6 is the test command register, and TR7 is the test data register.

• The test registers are privileged resources; in protected mode, the

MOV instructions that access them can only be executed at
privilege level 0

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 The Test Command Register (TR6)
• C: Command bit, two commands: ‘0’- write
entries into the TLB and ‘1’ perform TLB
lookups
• Linear Address:
 on a TLB write command, a TLB entry is
allocated to this linear address and the rest of
that TLB entry is set as per the values of TR7
& TR6
 on a TLB lookup command, the TLB is
interrogated as per this value and if one and
only one TLB entry matches, the rest of the
fields of TR6 & TR7 are set from the matching
TLB entry.
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• V: The Valid bit for this TLB entry. The TLB uses the
valid bit to identify entries that contain valid data.
Entries of the TLB that have not been assigned values
have zero in the valid bit. All valid bits can be cleared
by writing to CR3.
• D, D#: The dirty bit for/from the TLB entry
• U, U#: The U/S bit for/from the TLB entry
• W, W#: The R/W bit for/from the TLB entry
Meaning of D, U, and W Bit Pairs
86
 The Test Data Register (TR7)
Holds data read from or data to be written to the TLB

• Physical Address: This is the data field of the TLB. On a write to the TLB, the
TLB entry allocated to the linear address in TR6 is set to this value. On a TLB
lookup, if HT is set, the data field (physical address) from the TLB is read out to
this field. If HT is not set, this field is undefined.

• HT: For a TLB lookup, the HT bit indicates whether the lookup was a hit (HT <- 1)
or a miss (HT <- 0). For a TLB write, HT must be set to 1.

• REP: For a TLB write, selects which of four associative blocks of the TLB is to be
written. For a TLB read, if HT is set, REP reports in which of the four associative
blocks the tag was found; if HT is not set, REP is undefined.

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 Test Operations
 To write a TLB entry
• Move a doubleword to TR7 that contains the desired physical address, HT,
and REP values. HT must contain 1. REP must point to the associative block in
which to place the entry
• Move a doubleword to TR6 that contains the appropriate linear address, and
values for V, D, U, and W. Be sure C=0 for "write" command.

 To look up (read) a TLB entry

• Move a doubleword to TR6 that contains the appropriate linear address and
attributes. Be sure C = 1 for "lookup" command
• Store TR 7. If the HT bit in TR 7 indicates a hit, then the other values reveal
the TLB contents. If HT indicates a miss, then the other values in TR 7 are
indeterminate

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 Systems Instructions
1. Verification of pointer parameters:
• ARPL ── Adjust RPL
• LAR ── Load Access Rights
• LSL ── Load Segment Limit
• VERR ── Verify for Reading
• VERW ── Verify for Writing
2. Addressing descriptor tables:
• LLDT ── Load LDT Register
• SLDT ── Store LDT Register
• LGDT ── Load GDT Register
• SGDT ── Store GDT Register
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3. Multitasking:
• LTR ── Load Task Register
• STR ── Store Task Register
4. Coprocessing and Multiprocessing :
• CLTS ── Clear Task-Switched Flag
• ESC ── Escape instructions
• WAIT ── Wait until Coprocessor not
Busy
• LOCK ── Assert Bus-Lock Signal
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 Systems Instructions
5. Input and Output : 7. Debugging :
• IN ── Input • MOV ── Move to and from debug
• OUT ── Output INS ── Input String registers
• OUTS ── Output String
8. TLB testing :
• MOV ── Move to and from test registers
6. Interrupt control :
• CLI ── Clear Interrupt-Enable Flag 9. System Control:
• STI ── Set Interrupt-Enable Flag • SMSW ── Set MSW
• LIDT ── Load IDT Register • LMSW ── Load MSW
• SIDT ── Store IDT Register • HLT ── Halt Processor
• MOV ── Move to and from control
registers

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