GALACTROSE PRESENTING

Seminar
On
Asynchronous Chips

Submitted To: Submitted By:

College Officials Galactrose
CONTENTS

 INTRODUCTION
 PROBLEMS WITH SYNCHRONOUS
 Approach ASYNCHRONOUS LOGIC
 HOW DO THEY WORK?
 SOME FEATURES
 A CHALLENGING TIME
 CONCLUSION
 REFERENCES
INTRODUCTION

 Computer chips of today are synchronous.

 They contain a main clock, which controls the timing of
the entire chips.
 There are problems, however, involved with these
clocked designs that are common today.
 One problem is speed. A chip can only work as fast as
its slowest component.
Problems with Synchronous Approach

 Distributing the clock globally.

 Wastage of energy.
 Traverse the chip’s longest wires in one clock cycle.
 Order of arrival of the signals is unimportant.
 Clocks themselves consume lot of energy (~30%).
Asynchronous logic circuits

 Colckless chips/Asynchronous/self-timed circuits.

 Functions away from the clock.
 Different parts work at different speeds.
 Hand-off the result immediately.
Clock time cycle vs. clockless time cycle
RENDEZVOUS CIRCUITS
How do they work?

 No pure asynchronous chips are available.

 Uses handshake signals for the data exchange.
 Data moves only when required, not always.

◦ Minimizes power consumption.

◦ Less EMI  less noise  more applications.

◦ Stream data applications.

Some features

Integrated pipelining mode.

◦ Domino logic.

◦ Delay – insensitive.

Two different implementation details

◦ Dual rail.

◦ Bundled data.
Challenges
Interfacingbetween synchronous and
asynchronous
◦ Many devices available now are synchronous in
nature.
◦ Special circuits are needed to align them.
Lack of expertise.
Lack of tools.
Engineers are not trained in these fields.
Academically, no courses available.
CONCLUSION

Clocks have served the electronics design

industry very well for a long time, but
there are insignificant difficulties looming
for clocked design in future. These
difficulties are most obvious in complex
SOC development, where electrical noise,
power and design costs threaten to render
the potential of future process
technologies inaccessible to clocked
design.
REFERNCES

 www.google.com
 www.wikipedia.com
Thanks