Computer Organization and Architecture

PART II THE COMPUTER SYSTEM

Chapter 3 Top-Level View of Computer Function
and Interconnection
Chapter 4 Cache Memory
Chapter 5 Internal Memory
Chapter 6 External Memory
Chapter 7 Input / Output
Chapter 8 Operating System Support
William Stallings
Computer Organization
and Architecture
Chapter 3
A Top-Level View of Computer Function
and Interconnection
3.1 Computer Components
Three key concepts of von Neumann architecture:
• Data and instruction are stored in a single
read-write memory
(Main memory storing programs and data)
• ALU operating on binary data
• Memory are addressable
• Execution instruction from one to the next
1. Program Concept

Programming in Hardware

Sequence of
Arithmetic
Data Results
and Logic
Functions

Hardwired systems are inflexible

Programming in Software
Instruction Codes
• General purpose
hardware can do Instruction
different tasks, given Interpreter
correct control signals
• Instead of re-wiring, Control Signals

supply a new set of Data General-purpose Results

Arithmetic and
control signals
Logical Functions
What is a program?
• A sequence of steps
• For each step, an arithmetic or logical
operation is done
• For each operation, a different set of
control signals is needed

Program/Software:
A sequence of codes or instructions
2. Function of Control Unit
• For each operation a unique code is
provided
e.g. ADD, MOVE
• A hardware segment accepts the code and
issues the control signals
Instruction Instruction Control
Codes Interpreter Signals

1010…0110
3.2 Computer Function
• Basic function of a computer is execution of a
program
• A program is a sequence of instructions

Execution of instructions
Fetch: processor reads instruction from memory
one at a time.
Execution: processor interprets instruction and
perform operation
1. Basic Instruction cycle

• Two steps: Fetch & Execute

START Fetch Next Execute

HALT
Instruction Instruction

Fetch Cycle Execute Cycle

Instruction Cycle=fetch cycle + execute cycle

Fetch Cycle – Operations

• Program Counter (PC) holds address of next instruction to

fetch
• Processor fetches instruction from memory location pointed to by
PC
• Increment PC
o Unless told otherwise
• Instruction loaded into Instruction Register (IR)
• Processor interprets instruction and performs required actions
Execute Cycle Actions
• Perform operations
• According to the current instruction
Example of Program Execution
1/3
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 0 PC 300 1 9 4 0 3 0 10 PC
301 5 9 4 1 AC 301 5 9 4 1 AC
302 2 9 4 1 IR 302 2 9 4 1 1940 IR

940 0003 940 0003

941 0002 941 0002
Step 1 Step 2

4bits 12bits
Opcodes:
Instruction Opcode Address
0001 = Load AC from Memory
1bit 15bits 0010 = Store AC to Memory
Operand S Magnitude 0101 = Add to AC from Memory
Example of Program Execution
2/3
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 1 PC 300 1 9 4 0 3 0 12 PC
301 5 9 4 1 0003 AC 301 5 9 4 1 00 00 00 53 AC
302 2 9 4 1 IR 302 2 9 4 1 5941 IR

940 0003 940 0003 3+2=5

941 0002 941 0002 ALU
Step 3 Step 4

4bits 12bits
Opcodes:
Instruction Opcode Address
0001 = Load AC from Memory
1bit 15bits 0010 = Store AC to Memory
Operand S Magnitude 0101 = Add to AC from Memory
Example of Program Execution
3/3
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 2 PC 300 1 9 4 0 3 0 32 PC
301 5 9 4 1 0005 AC 301 5 9 4 1 0 0 0 5 AC
302 2 9 4 1 IR 302 2 9 4 1 2941 IR

940 0003 940 0003

941 0002 941 0002
Step 5 Step 6

4bits 12bits
Opcodes:
Instruction Opcode Address
0001 = Load AC from Memory
1bit 15bits 0010 = Store AC to Memory
Operand S Magnitude 0101 = Add to AC from Memory
2. Instruction Cycle State Diagram

Instruction Operand
fetch Operand
fetch Store

Multiple Multiple
Operands Results

Instruction Instruction Operand Data Operand

address operation address Operation address
calculating decoding calculating calculating

Instruction Complete Return for String

Fetch Next Instruction or Vector Data
3. Interrupts
• Mechanism by which other modules (e.g.
I/O, memory) may interrupt normal
processing of processor
• Classes of Interrupts
• Program: e.g. overflow, division by zero
• Timer: Generated by timer within processor
• I/O: Generated by I/O controller
• Hardware failure: e.g. memory parity error
Interrupt: a way to improve processing efficiency
Program Flow of Control
Program Flow of Control No interrupts
User Program I/O Program

① ④

I/O Command
WRITE OP

② ⑤

WRITE END

WRITE
Program Flow of Control With interrupts
User Program I/O Program

① ④

WRITE I/O Command

2a OP
2b
＊
Interrupt handler
WRITE
3a ⑤
＊
3b
END

WRITE
Short I/O wait
 OP

OP

 Ta = T1+T4+TOP2+T5+T2+T4+TOP3+T5+T3 T2a /Top2 ; T3a /Top3

= T1+T2+T3+2*T4+2*T5+TOP2+TOP3 OVERLAP
 Tb = T1+T4+T2a+T5+T2b+T4+T3a+T5+T3b in time
= T1+T2+T3+2*T4+2*T5
Program Flow of Control With interrupts
User Program I/O Program

① ④

WRITE I/O Command

OP
②
WRITE Interrupt handler

⑤
③
END

Long I/O wait

WRITE
Interrupt Process
• An interrupt of User Program
the normal 1
2
sequence of 3
Interrupt
execution
handler
• Interrupt
processing Interrupt I
I+1
• Execution Occurs Here

resume
Interrupt Cycle -Operations
-- Added to instruction cycle --
• Processor checks for interrupt request
o Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
o Suspend execution of current
o Save context
o Set PC to start address of interrupt handler routine
o Process interrupt
o Restore context and continue interrupted program
Instruction Cycle (with Interrupts) - State
Diagram

Instruction Operand
fetch Operand
fetch Store

Multiple Multiple
Operands Results

Instruction Operand Data Operand

Instruction address Operation address Interrupt Interrupt
operation Check
address decoding calculating calculating
calculating

No
Instruction Complete Return for String
Interrupt
Fetch Next Instruction or Vector Data
Multiple Interrupts
• Disable interrupts
• Processor will ignore further interrupts whilst
processing one interrupt
• Interrupts remain pending and are checked after
first interrupt has been processed
• Interrupts handled in sequence as they occur
• Define priorities
• Low priority interrupts can be interrupted by
higher priority interrupts
• When higher priority interrupt has been processed,
processor returns to previous interrupt
Multiple Interrupts – Sequential
User Program Interrupt Handler X

Interrupt Handler Y
Multiple Interrupts – Nested

User Program Interrupt Handler X

Interrupt Handler Y
3.3 Interconnection Structures
• All the units must be connected
• Different types of connection for different
types of units
o Memory
o Input/Output
o CPU
Interconnection Structures:
The collection of paths connecting the
various modules
1. Memory Connection

• Receives addresses (of locations)

• Receives and sends data
• Receives control signals
o Read
o Write
2. Input/Output Connection(1)
--Similar to memory from computer’s viewpoint--
• Receives addresses (of locations/ports)
• Receives and sends data (with CPU)
• Receives control signals from CPU
o Read
o Write
Input/Output Connection(2)

• Receives and sends data (with peripherals/external

devices)
• Send interrupt signals (to CPU)
3. CPU Connection

• Specify target locations (address)

• Reads instruction and data
• Writes out data (after processing)
• Sends control signals to other units
• Receives interrupts
3.4 Bus Interconnection

• There are a number of possible interconnection systems

• Single and multiple BUS structures are most common
e.g. Control/Address/Data bus (PC)
e.g. Unibus (DEC-PDP)
1. What is a Bus?

• A communication pathway connecting two

or more devices
• Usually broadcast
• Often grouped
o A number of channels/lines in one bus
o e.g. 32 bit data bus is 32 separate single bit
channels
• Power lines may not be shown
2. What is a System Bus?

• A bus that connects major computer

components (Processor, memory, I/O)

e.g. ISA 、 MCA 、 EISA 、 VESA,PCI 、 AGP 、

IEEE1394 、 USB
3. Three Groups of Bus

Data Bus
• Data lines of a bus
• Carries data
o Remember that there is no difference between “data” and
“instruction” at this level
• Bits be transferred at a time
• Width is a key determinant of performance
o 8, 16, 32, 64 bit
Address bus

• Identify location of source/destination data

e.g. CPU needs to read an instruction (data) from a given
location in memory
• Bus width determines maximum memory capacity of
system (how many locations)
e.g. 8080 has 16 bit address bus giving 64k(=216) address
space
Control Bus

• Control and timing information

o Memory read/write signal
o I/O read/write signal
o Interrupt request
o Clock signals
• Typical control lines
o Memory & I/O Read/Write
o Bus request/grant
o Interrupt request/ ACKnowledge
o Reset, Clock …
Bus Interconnection Scheme

CPU Memory Memory I/O I/O

Control lines
Data lines
Address lines
Operation of the Bus

• Obtain the use of the bus

• Transfer data via the bus
Disadvantage of Bus

• Lots of devices on one bus leads to:

• Propagation delays
Long data paths mean that co-ordination of bus use can adversely affect
performance
• Bus may become a bottleneck If aggregate data transfer
approaches bus capacity
• Most systems use multiple buses to overcome these problems
4. Multi-Bus Hierarchies
Single Bus Problems
• Lots of devices on one bus leads to:
o Propagation delays
Long data paths mean that co-ordination of
bus use can adversely affect performance
o Bus may become a bottleneck If aggregate
（合计） data transfer approaches bus
• Mostcapacity
systems use multiple buses to overcome
these problems
Traditional (ISA) (with cache)*
Local Bus
Processor Cache

Local I/O
Main
controller
Memory

System Bus

Network Expansion Serial

SCSI Bus Interface Modem

Expansion Bus
5. Elements of Bus Design

• Bus Type
• Method of Arbitration
• Timing
• Bus Width
Bus Types
• Dedicated
Separate data & address lines
• Multiplexed
o Shared lines
o Address valid or data valid control line
o Advantage - fewer lines
o Disadvantages
More complex control
Ultimate performance
Bus Arbitration

• More than one module controlling the bus

e.g. CPU and DMA controller
• Only one module may control bus at one time
• Arbitration may be centralised or distributed

Master device
Slave device
Centralised Arbitration

• Single hardware device controlling bus access

• Bus Controller
• Arbiter
• May be part of CPU or separate
Distributed Arbitration

• Each module may claim the bus

• Control logic on all modules
Timing

• Co-ordination of events on bus

• Synchronous
o Events determined by clock signals
o Control Bus includes clock line
o A single 1-0 is a bus cycle
o All devices can read clock line
o Usually sync on leading edge
o Usually a single cycle for an event
Synchronous Timing Diagram*
Asynchronous Timing Diagram*
Bus Width

• Data Bus Width

• Address Bus Width
Chapter 3 Homework
3.1 Describe the following concepts:
Software
Computer Bus
3.2 Describe the concepts of von Neumann machine.
3.3 Describe the operations of Fetch Cycle.
3.4 Describe the operations of Interrupt Cycle.
3.5 Describe the difference between Data Bus, Address
Bus and Control Bus.
3.6 Describe the elements of Bus design.